Dissemination Communication Press Repository

-- results

Author

Abraham Ruiz

Adrià Armejach

Adrian Cristal

Agnese Reina

Agneza Krajna

Alberto Gonzales

Alen Duspara

Alessandro Cilardo

Alessandro Ottaviano

Alexandru Calotoiu

Alireza Monemi

Amir Charif

Andrea Bartolini

Andrea Bocco

Andrea Domenici

Andrea Tilli

Andreas Kurth

Antoni Portero

Antonio Andreini

Antonio Del Vecchio

Antonio Mastrandrea

Arief Wicaksana

Asif Ali

Authors listed in alphabetical order:

Benedetta Mazzoni

Benoît Dupont de Dinechin

Berk Saglam

Bernd Mohr

Biagio Cosenza

Bogdan Trasnea

Branimir Malnar

Carles Hernandez

Carlos Álvarez

Carlos Falquez

Carlos Rojas

César Fuguet-Tortolero

César Hernandez

Chi Zhang

Christian Conficoni

Christian Feldmann

Christos Zonios

Cinzia Bernardeschi

Claudio A. Ardagna

Claudiu Pozna

Corrado Bonfanti

Cosmin Ginerica

Craig Prunty

Daniel Hofman

Daniel Jiménez-González

Daniele Cesarini

Daniele Rossi

Daniele Simoni

Davide Lengani

Davide Rossi

Denis Dutoit

Dirk Pleiter

Dominik Reinhardt

Dominique Bolignano

Emanuele Ruffaldi

Enrico Reggiani

Enrique Vallejo

EPI

EPI Forum slides

Eric Guthmuller

Eric Monchalin

Estela Suarez

Etienne Walter

EuroHPC JU

Fabian Kempf

Fabian Kreß

Fabian Schätzle

Fabian Schuiki

Fabio Banchelli

Fabrizio Magugliani

Fatma Jebali

Federico Cosimo Lapenna

Federico Ficarelli

Federico Rossi

Filippo Mantovani

Florian Zaruba

Florin Gogianu

Frances Moll

Francesc Martínez Palau

Francesco Falaschi

Francesco Minervini

Francisco J. Cazorla

Frank Badstuebner

Frank K. Gürkaynak

Gabriel Falcao

Georgios Ieronymakis

Ghassem Jaberipur

Gianluca Dini

Gigel Macesanu

Giovanni Agosta

Giovanni Bambini

Giuseppe Lettieri

Guillem López-Paradís

Henrique Yano

Igor Piljić

Ihsane Tahir

Imen Baili

Ivan Diaz

Iván Pérez

Ivan Sarno

Ivan Spisso

Ivan Vargas

Jacopo Belli

Jakub Beránek

Jaume Abella

Jean-Marc Denis

Jérôme Fereyre

Jesus Labarta

Joan Cabre

Joan Marimon

João Domingos

João Vieira

Joel Criado

John Davis

John L. Gustafson

Jonnatan Mendoza

Jorge Alejandro Nocua Cifuentes

Josep Sans

Josip Knezović

Josue Quiroga

Juan Miguel De Haro

Julian Hoefer

Julian Pavon

Jürgen Becker

Katarina Vukušić

Klas Moreau

Kristijan Poje

Leon Dragić

Leonel Sousa

Leonhard Kraft

Leonidas Kosmidis

Lilia Zaourar

Lina Khoirunisya

Luca Baldanzi

Luca Benini

Luca Bertaccini

Luca Crocetti

Luca Fanucci

Luca Valente

Luca Zulberti

Lucian Busoniu

Luigi Leonardi

Luigi Treccozzi

Luis Bertran Alvarez

Luís Crespo

Maicol Ciani

Manolis Marazakis

Marc Casas

Marc Dominguez

Marco Aldinucci

Marco Cococcioni

Marco Danelutto

Marco Rasori

Mario Brčić

Mario Kovač

Mario Rodriguez

Marta Garcia-Gasulla

Marti Torrents

Martin Molan

Massimo Torquati

Mate Kovač

Mateo Valero

Matheus Cavalcante

Matteo Bertolucci

Matteo Lo Gerfo

Matteo Perotti

Matthias Traub

Maurizio Palmieri

Mauro Olivieri

Michael Rogenmoser

Michele La Manna

Mihai Zaha

Miquel Moretó

Mirko Cestari

Mohsen Barzegar

Mohsen Sadegh

Mustapha Bouhali

Nam Ho

Nehir Sonmez

Neiel Leyva

Nicasio Canino

Nick Kossifidis

Nicolas Ventroux

Nikolaos Dimou

Nikolaos Kallimanis

Nuno Neves

Nuno Roma

Oliver Jesorsky

Oscar Palomar

Osman Unsal

Oumaima Matoussi

Pablo Vizcaino

Patrice Hameau

Paul Scheffler

Pedro Tomás

Per Stenström

Pericle Perazzo

Peter Hsu

Philipp Merz

Philippe Notton

Pietro Nannipieri

Polydoros Petrakis

R. Ignacio Genovese

Raffaele Montella

Ramón Beivide

Raúl Peñacoba

Renaud Stevens

Ricardo Chaves

Riccardo Alidori

Robert Balas

Roberto Esposito

Roberto Giorgi

Roger Espasa

Roger Ferrer

Roger Figueras

Rogério Paludo

Romain Dolbeau

Sahar Moradi Cherati

Salvatore Di Girolamo

Samuel Riedel

Sébastien Le Duc

Sergi Alcaide

Sergio Saponara

Simone Benatti

Sorin Grigorescu

Stefan Mach

Stefano Di Matteo

Stepan Nassyr

Stephan Stilkerich

Stéphane Cordova

Stephane Strahm

Tanguy Sassolas

Tanja Harbaum

Thomas Benz

Tiago Rocha

Tien Tu Vo

Tim Hotfilter

Timo Schneider

Torsten Hoefler

Vasileios Tenentes

Vassilis Papaefstathiou

Víctor Jimenez

Victor Lopez

Vito Luca Guglielmi

William Fornaciari

Xavier Teruel

Ying-Chih Yang

Yves Durand

Type

Book chapter

Conference Paper

Conference proceedings

Deliverable

Factsheet

Flyer

Journal Article

Podcast

Poster

Presentation

Press

Press coverage

Press release

Publication - magazine

Roll-up

Tutorial

Workshop

Keyword

accelerator

architecture

automotive

co-design

common platform

EPAC architecture

EuroHPC

FPU

hpc landscape

open HW

PCIe daughter board

RISC-V

SDV

security

semiconductor

software

tutorial

Year

2018

2019

2020

2021

2022

2023

2024

2025

Phase

Phase 1

Phase 2

RTL Flow for the Power Side-Channel Resilience Assessment of a Post-Quantum SHA-3 Accelerator

Authors listed in alphabetical order:

13th International Conference on Modern Circuits and Systems Technologies (MOCAST)

Conference Paper

2024

Phase 2

On hardware acceleration of quantum-resistant FOTA systems in automotive

Authors listed in alphabetical order:

Computers and Electrical Engineering

Journal Article

2024

Phase 2

Data Prefetching on Processors with Heterogeneous Memory

Antoni Portero

Authors listed in alphabetical order:

Exploiting Vector Code Semantics for Efficient Data Cache Prefetching

Adrià Armejach

Authors listed in alphabetical order:

Francesc Martínez Palau

Marc Casas

Marti Torrents

ICS '24: Proceedings of the 38th ACM International Conference on Supercomputing

Conference Paper

2024

Phase 2

Graph Computing on Long Vector Architectures (Yes, It Works!)

Authors listed in alphabetical order:

HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement

Authors listed in alphabetical order:

Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures

Authors listed in alphabetical order:

CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms

Authors listed in alphabetical order:

A PUF-Based Secure Boot for RISC-V Architectures

Authors listed in alphabetical order:

Federico Cosimo Lapenna

Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative

Authors listed in alphabetical order:

NDPmulator: Enabling Full-System Simulation for Near-Data Accelerators From Caches to DRAM

Authors listed in alphabetical order:

Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments

Authors listed in alphabetical order:

gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation

Authors listed in alphabetical order:

IEEE Computer Architecture Letteres

Journal Article

2023

Phase 2

Decoding-free Two-Input Arithmetic for Low-Precision Real Numbers

Authors listed in alphabetical order:

Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative

Authors listed in alphabetical order:

IEEE Transactions on Computers

Journal Article

2023

Phase 2

Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators

Authors listed in alphabetical order:

At the EPI forum in Barcelona eeNews Europe discussed the state of the initiative with Eric Monchalin, the chair of the European Processor Initiative

Press coverage

2024

Phase 2

ARM and RISC-V are at the helm of the European Processor Initiative

Press coverage

2024

Phase 2

The European Processor Initiative aims to bring together research, design and manufacturing of a home-grown European processor

Press coverage

2024

Phase 2

EPI Forum in Barcelona

Press release: EPI Forum in Barcelona, October 9-10, Barcelo Sants hotel

AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads

Authors listed in alphabetical order:

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Conference proceedings

2023

Phase 2

ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration

Lecture Notes in Computer Science

Conference proceedings

2022

Phase 2

A High-Performance, Energy-Efficient Modular DMA Engine Architecture

IEEE Transactions on Computers

Journal Article

2023

Phase 2

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

International Journal of Parallel Programming

Journal Article

2024

Phase 2

Trading Performance, Power, and Area on Low-Precision Posit MAC Units for CNN Training

Conference proceedings

2023

Phase 2

Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation

Andrea Bocco

César Fuguet-Tortolero

Sparse Matrix-Vector Multiplication Based on Online Arithmetic

Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor

Andrea Bocco

César Fuguet-Tortolero

Conference proceedings

2022

Phase 2

OpenHW CORE-V High-Performance, Out-of-Order, L1 Data Cache (HPDCache)

César Fuguet-Tortolero

Bologna, Italy

Conference proceedings

2023

Phase 2

What We Know about Alice Recoque, Europe’s Second Exascale System

Press coverage

2024

Phase 2

Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V

Vassilis Papaefstathiou

Conference Paper

Conference proceedings

2023

Phase 2

Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency

COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores

Jorge Alejandro Nocua Cifuentes

Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study

Vassilis Papaefstathiou

Conference Paper

2023

Phase 2

Supporting RISC-V Performance Counters Through Linux Performance Analysis Tools

A Hardware-Centric Approach to Increase and Prune Regular Activation Sparsity in CNNs

$400m RISC-V design centre for Barcelona

Press coverage

2022

Phase 2

Hewlett Packard Enterprise and SiPearl Partner to Develop HPC Solutions with European Processors and Accelerate Europe’s Adoption of Exascale Supercomputers

Press coverage

2022

Indigenous HPC: What It Means and Why Now

Press coverage

2022

Phase 2

Joined up thinking: Europe to oversee trio of projects for homegrown chips, HPC gear

Press coverage

2022

Phase 2

EuroHPC Launches 3 New Research and Innovation Projects

Press coverage

2022

Phase 2

E4 Contributes to the Success of the European Processor Initiative

Press coverage

2022

Phase 2

E4 helps EPI in chip and HPC independence

Press coverage

2022

Phase 2

French cybersecurity firm ProvenRun gets €15M from Tikehau Capital, others for IoT security advancements

Press coverage

2023

Phase 2

European Processor Initiative (EPI) partner SiPearl will provide its general purpose processor for Europe’s first EuroHPC exascale supercomputer JUPITER

Press coverage

2023

Phase 2

Održan Dan Hrvatskog centra kompetencija za HPC

Press coverage

2023

Phase 2

European Processor Initiative achieves significant sovereignty contribution

Press coverage

2023

Phase 2

European Processor Initiative Drives Digital Sovereignty Forward with JUPITER

Press coverage

2023

Phase 2

The EPAC1.5 – a significant milestone in high-performance computing

Press coverage

2023

Phase 2

The EPAC1.5 – a significant milestone in high-performance computing

Press coverage

2023

Phase 2

European Processor Initiative partner SiPearl will provide its general purpose processor for Europe’s first EuroHPC exascale supercomputer JUPITER

Press coverage

2023

Phase 2

Why Europe must have a home-grown HPC processor

Press coverage

2023

Phase 2

Europe’s first exascale supercomputer will use Arm processors with Nvidia GPU nodes

Press coverage

2023

Phase 2

The European Union announces Jupiter, its first supercomputer that exceeds exaFLOP power

Press coverage

2023

Phase 2

European high performance processor designer SiPearl has won its first major customer in JUPITER, the European exascale supercomputer to be built in Germany

Press coverage

2023

Phase 2

EU Unveils Its First ExaFlop Supercomputer, Featuring The Power Of ARM & NVIDIA

Press coverage

2023

Phase 2

JUPITER Exascale Supercomputer, lead customer for SiPearl

Press coverage

2023

Phase 2

Europe’s exascale supercomputer in its starting blocks

Press coverage

2023

Phase 2

Jupiter exascale supercomputer to be built by Atos’ Eviden

Press coverage

2023

Phase 2

An Eviden led consortium to build Europe’s first exascale supercomputer

Press coverage

2023

Phase 2

EU Grabs ARM for First ExaFLOP Supercomputer, x86 Misses Out

Press coverage

2023

Phase 2

EuroHPC Amplifies European Research and Industry with JUPITER’s Exascale Potential

Press coverage

2023

Phase 2

HPC: Enabling Science at Scale

Press coverage

2023

Phase 2

An open source cloud software ecosystem for the EPI hardware

Press coverage

2023

Phase 2

The Golden Age of Custom Silicon Draws Near: Part 2

Press coverage

2023

Phase 2

ACM Europe Summer School on HPC Computer Architectures for AI and Dedicated Applications

Press coverage

2023

Configurable 64-bit RISC-V IP Targets Machine Learning, Other Advanced Apps

Press coverage

2023

Phase 2

RISC-V CPUs: Enabling Processor Innovation

Press coverage

2023

Phase 2

Vivian Blanchard Named VP Hardware R&D at SiPearl

Press coverage

2023

Phase 2

EuroHPC Executive Director Talks Europe’s Supercomputing Future

Press coverage

2023

Phase 2

Semidynamics launches world’s first fully customisable RISC-V IP cores

Press coverage

2023

Phase 2

SiPearl raises €90m for Rhea European supercomputer chip

Press coverage

2023

Phase 2

SiPearl Raises $98.3M in Series A Funding to Launch Rhea HPC Microprocessor

Press coverage

2023

Phase 2

SiPearl Raises $98.3M in Series A Funding to Launch Rhea HPC Microprocessor

Press coverage

2023

Phase 2

SiPearl Raises $98.3M in Series A Funding to Launch Rhea HPC Microprocessor

Press coverage

2023

Phase 2

SiPearl Raises $98.3M in Series A Funding to Launch Rhea HPC Microprocessor

Press coverage

2023

Phase 2

SiPearl Raises $98.3M in Series A Funding to Launch Rhea HPC Microprocessor

Press coverage

2023

Phase 2

A Not So Simple Matter of Software

Press coverage

2023

Phase 2

Étienne Walter on next steps for the European Processor Initiative

Press coverage

2023

Phase 2

Google wants to make RISC-V one of the core architectures for Android – on par with Arm

Press coverage

2023

Phase 2

SiPearl and Samsung Form Alliance to Enhance European Processor Technologies with HBM Integration

Press coverage

2024

Phase 2

SiPearl partners with Samsung Electronics for built-in HBM in Rhea

Press coverage

2024

Phase 2

SiPearl partners with Samsung for built-in HBM in Rhea

Press coverage

2024

Phase 2

SiPearl chooses Italy to open its third international subsidiary

Press coverage

2024

Phase 2

SiPearl unveils key features of the Rhea 1 to accelerate HPC and AI inference

Press coverage

2024

Phase 2

80 Arm Neoverse V1 cores and in-package memory for SiPearl MCU

Press coverage

2024

Phase 2

SiPearl: Partnership with Samsung Electronics for built-in HBM in Rhea

Press coverage

2024

Phase 2

SiPearl’s Rhea1 Delivers Exceptional Compute Performance with 80 Arm Neoverse V1 Cores

Press coverage

2024

Phase 2

SiPearl unveils features of Rhea1 HPC / AI inference processor

Press coverage

2024

Phase 2

SiPearl reveals release date for Rhea-2 HPC chip

Press coverage

2024

Phase 2

SiPearl’s Rhea2 CPU Added to Roadmap: Second-Gen European CPU for HPC

Press coverage

2024

Phase 2

Next Euro HPC Chip Coming Next Year Will Be in 2026 EU Exascale System

Press coverage

2024

Phase 2

BSC Hosts 2nd European Memory Systems Forum, Uniting Global Experts in Barcelona

Press coverage

2024

Phase 2

European Union Seeks Chip Sovereignty Using RISC-V

Press coverage

2024

Phase 2

SMART TECH – Microprocesseur : comment avance le projet de HPC européen?

Press coverage

2024

Phase 2

France’s electronics evolution and sustainable future

Press coverage

2024

Phase 2

HPC Podcast powered by EXCELLERAT – European Processor Initiative

Press coverage

2024

Phase 2

Invité IT de la semaine : Philippe Notton, SiPearl

Press coverage

2024

Phase 2

Europe ‘on a par with US’ as installation of its first exascale supercomputer nears completion

Press coverage

2024

Phase 2

LEAK: EU Commission prepares ‘strategic framework’ to boost AI start-ups, generative AI uptake

Press coverage

2024

Phase 2

EU puts its weight behind home-grown processor for its new €273M supercomputer

Press coverage

2024

Phase 2

First Steps towards Efficient Genome Assembly on ARM-Based HPC

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit

European Processor Initiative Demonstration of Integrated Semi-Autonomous Driving System

Conference proceedings

2023

Phase 2

VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library

A Survey on Attribute-Based Encryption Schemes Suitable for the Internet of Things

IEEE Internet of Things Journal

Journal Article

2023

Phase 2

Reusable Verification Environment for a RISC-V Vector Accelerator

Conference proceedings

2023

Phase 2

JUPITER Exascale Supercomputer, lead customer for SiPearl

Press coverage

2023

Phase 2

Press release: European Processor Initiative announces the successful bring-up of the EPAC1.5 acceleration chip

Press release: European Processor Initiative partner SiPearl will provide its general purpose processor for Europe’s first EuroHPC exascale supercomputer JUPITER

SiPearl has raised €90m in financing which will allow the commercialisation of Rhea

Press coverage

2023

Phase 2

European Processor Initiative Yearly Public Report (2022)

Functional verification of a RISC-V vector accelerator

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM

Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA

Conference proceedings

2022

Phase 2

On the Hardware–Software Integration in Cryptographic Accelerators for Industrial IoT

Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source

VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Journal Article

2022

Phase 2

Experimental Results of Vectorized Posit-Based DNNs on a Real ARM SVE High Performance Computing Machine

EPI @ HiPEAC 2023

Europe to Dish out €270 Million to Build RISC-V Hardware and Software

Press coverage

2022

Phase 2

SiPearl works with AMD on GPU support for Arm HPC chip

Press coverage

2022

Phase 2

RISC-V Is Far from Being an Alternative to x86 and Arm in HPC

Press coverage

2022

Phase 2

Europe’s Chip Sovereignty Altering US Chip Companies’ Exascale Approach

Press coverage

2022

Phase 2

La strategia europea e la difficile autonomia

Press coverage

2022

Phase 2

EPI @ SEDEX 2022

EPI @ CECAM 2022

EPI @ REHE 2022

Daniele Cesarini

13th International Conference on Relativistic Effects in Heavy-Element Chemistry and Physics

Presentation

2022

Phase 2

EPI @ 2022 ACM Europe Summer School

Jesus Labarta

Roger Ferrer

2022 ACM Europe Summer School

Presentation

2022

Phase 2

Q&A with EPI Chair Eric Monchalin, an HPCwire Person to Watch in 2022

Press coverage

2022

Phase 2

Tech Focus: Software tools

Press coverage

2022

Phase 2

Decoupling processor and memory hierarchy simulators for efficient design space exploration

RAPIDO 2022 workshop (HiPEAC Conference)

Conference Paper

2022

Phase 2

Small reals representations for Deep Learning at the edge: a comparison

2022 edition of the Conference on Next Generation Arithmetic (CoNGA'22)At: Singapore

Conference Paper

2022

Phase 2

A Survey on Attribute-Based Encryption Schemes Suitable for the Internet of Things

IEEE Internet of Things Journal

Journal Article

2022

Phase 2

Compiling for Vector Extensions with Stream-based Specialization

NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator

Leonel Sousa

Rogério Paludo

IEEE Transactions on Circuits and Systems I: Regular Papers

Journal Article

2022

Phase 2

Unified Posit/IEEE-754 Vector MAC Unit for Transprecision Computing

IEEE Transactions on Circuits and Systems II: Express Briefs

Journal Article

2022

Phase 2

Strong-armed into HPC, like it or not

Press coverage

2022

Phase 2

EPI @ HiPEAC Conference in Budapest

EPI @ ISCA 2022

EPI @ HiPEAC 2022

EPI @ MPSoC 2022

EPI @ HiPEAC 2022 Conference

Klas Moreau

HiPEAC 2022 Conference

Presentation

2022

Phase 2

The IoT Radar Interview with Eric Monchalin

Press coverage

2022

Phase 2

As LUMI Launches, a Look at the State of EuroHPC

Press coverage

2022

Phase 2

Demystifying the RISC-V Linux software stack

Nick Kossifidis

Spring 2022 RISC-V Week

Presentation

2022

Phase 2

Atrevido: SemiDynamics Out-of-Order RISC-V Core

Roger Espasa

Spring 2022 RISC-V Week

Presentation

2022

Phase 2

VRP/VXP: VaRiable eXtended Precision RISC-V Accelerator for High-Precision

César Fuguet-Tortolero

Spring 2022 RISC-V Week

Presentation

2022

Phase 2

The RISC-V based Stencil Tensor Accelerator of EPI

Matheus Cavalcante

Spring 2022 RISC-V Week

Presentation

2022

Phase 2

Vitruvius: An Area-Efficient RISC-V Decoupled Vector Accelerator for High Performance Computing

Francesco Minervini

Spring 2022 RISC-V Week

Presentation

2022

Phase 2

The Accelerator Tile of European Processor Initiative

Jesus Labarta

Spring 2022 RISC-V Week

Presentation

2022

Phase 2

RISC-V based Power Management Unit for an HPC processor

Andrea Bartolini

Spring 2022 RISC-V Week

Presentation

2022

Phase 2

SW Toolchain for RISC-V Vector Extensions

Roger Ferrer

Spring 2022 RISC-V Week

Presentation

2022

Phase 2

EPI @ HPCSE 2022

Daniele Cesarini

The High Performance Computing in Science and Engineering 2022 conference (HPCSE 2022)

Presentation

2022

Phase 2

EPI @ ISC22

EPI @ ISCAS 2022

SiPearl Emerging as Heavyweight for ‘Made in Europe’ Chips

Press coverage

2022

Phase 2

Home-grown Euro chipmaker SiPearl signs deal with HPE, Nvidia

Press coverage

2022

Phase 2

Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs

Carlos Álvarez

Daniel Jiménez-González

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Conference Paper

2022

Phase 2

EPI @ 19th ACM International Conference on Computing Frontiers (CF’22)

Federico Ficarelli

Martin Molan

Mohsen Sadegh

19th ACM International Conference on Computing Frontiers (CF'22)

Presentation

2022

Phase 2

HPE Announces New HPC Factory in Czech Republic

Press coverage

2022

Phase 2

Innovation at scale

Spring 2022 digital issue

Press coverage

2022

Phase 2

European Processor Initiative will have ZeroPoint IP in their chip

Press coverage

2022

Phase 2

Ransomware: who pays on the rise – European processor – Digital Service Act

Press coverage

2022

Phase 2

EPI SGA2 – Building Europe’s high performance computing capabilities

Leading the way in European Supercomputing

Press coverage

2022

Phase 2

Oil And Gas Industry To Get Its Own Stencil Tensor Accelerator

Press coverage

2022

Phase 2

EPI at UBA

EPI at DATE 2022

EPI at HPC User Forum

People to Watch 2022

Press coverage

2022

Phase 2

Intel to spend €17bn on chip mega-factory in Germany

Press coverage

2022

Phase 2

Server Microprocessor Market Outlook and Growth Stance Forecast 2022-2031

Press coverage

2022

Phase 2

SiPearl Picks Ansys’s Power Signoff Solution for European Supercomputer Chip

Press coverage

2022

Phase 2

Press release: 3 new R&I projects to boost the digital sovereignty of Europe

E4 contributes to the success of the European Processor Initiative

Press coverage

2022

Phase 2

3 new R&I projects to boost the digital sovereignty of Europe

Press coverage

2022

Phase 2

European Processor Initiative – Europe’s Approach to Exascale Computing

Agneza Krajna

Alen Duspara

Benoît Dupont de Dinechin

Shooting for the moon: Taking European technology to the next level

Press coverage

2022

Phase 2

EC president promises European Chips Act to quadruple homegrown production by 2030

Press coverage

2022

Phase 2

EPI at IEEE Computer Society Israel Webinar

Jesus Labarta

IEEE Computer Society Israel Webinar

Presentation

2022

Phase 2

Europe ups the ante: chips for autonomous driving

Press coverage

2022

Phase 2

EPI Announces Successful Conclusion of European Processor Initiative Phase One

Press coverage

2021

Phase 1

Press release: Successful conclusion of European Processor Initiative Phase One

EPI at International CAE Conference and Exhibition

Fabrizio Magugliani

International CAE Conference and Exhibition

Presentation

2021

Phase 1

EPI at RISC-V Summit 2021

SiPearl Affirms Exascale Plans and Key Partnerships at SC21

Press coverage

2021

Phase 1

E4 Announces the RISC-V-Based Monte Cimone Cluster

Press coverage

2021

Phase 1

EPI at Supercomputing21

EPI at RISC-V Forum: Vector and Machine Learning

Roger Espasa

RISC-V Forum: Vector and Machine Learning

Presentation

2021

Phase 1

At SC21, Experts Ask: Can Fast HPC Be Green?

Press coverage

2021

Phase 1

EPI at National Information Day Horizon Europe Cluster 4 – Digital, Industry and Space 2021

Mario Kovač

National Information Day Horizon Europe Cluster 4 - Digital, Industry and Space 2021

Presentation

2021

Phase 1

Greek institute pioneers cutting-edge EU chip technology

Press coverage

2021

Phase 1

PIugSMART: a pluggable open-source module to implement multihop bypass in networks-on-chip

NOCS '21: Proceedings of the 15th IEEE/ACM International Symposium on Networks-on-Chip

Conference Paper

2021

Phase 1

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator

Adrià Armejach

Guillem López-Paradís

Miquel Moretó

ICPP 2021: 50th International Conference on Parallel Processing

Conference Paper

2021

Phase 1

EPI at CSW Autumn 2021

Benoît Dupont de Dinechin

A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)

Conference Paper

2021

Phase 1

EPI at Seminari ‘’in pillole’’ European High Performance Computing Joint Undertaking

Seminari ‘’in pillole’’ European High Performance Computing Joint Undertaking

Workshop

2021

Phase 1

A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications

IEEE Transactions on Emerging Topics in Computing

Journal Article

2021

Phase 1

EPI at MICRO 2021: 54th IEEE/ACM International Symposium on Microarchitecture

Per Stenström

MICRO 2021: 54th IEEE/ACM International Symposium on Microarchitecture

Presentation

2021

Phase 1

El BSC dissenya un xip de codi obert que triplica la velocitat del seu antecessor

Press coverage

2021

Phase 1

La UPC y el Barcelona Supercomputing Centre desarrollan un chip importante para avanzar hacia la soberanía tecnológica europea

Press coverage

2021

Phase 1

EPI at 27th International European Conference on Parallel and Distributed Computing

Mario Kovač

27th International European Conference on Parallel and Distributed Computing

Presentation

2021

Phase 1

EU-Prozessor-Testchip

Press coverage

2021

Phase 1

Exascale-chips van eigen bodem

Press coverage

2021

Phase 1

EPI at ACM Europe Summer School

Jesus Labarta

Mauro Olivieri

Roger Espasa

ACM Europe Summer School

Presentation

2021

Phase 1

EPI at ApplePies 2021

Press release: EPI EPAC1.0 RISC-V Test Chip Samples Delivered

Synch: A framework for concurrent data structures and benchmarks

Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

An OpenMP Free Agent Threads Implementation

Conference proceedings

2021

Phase 1

EPI @ SIE2021

EPI at IEEE SB POLITO

Unlimited Vector Extension with Data Streaming Support

ISCA2021, IEEE Xplore

Conference Paper

Conference proceedings

2021

Phase 1

Interview with Philippe Notton at BFM Business

Press coverage

2021

Phase 1

L’interview de Philippe Notton (SIPEARL) par Cécilia Severi

Press coverage

2021

Phase 1

Europe’s Evolving View of “Continental Exascale”

Press coverage

2021

Phase 1

Hyperion Research Announces Agenda for 2nd Virtual HPC User Forum

Press coverage

2021

Phase 1

NoC Performance Model for Efficient Network Latency Estimation

Oumaima Matoussi

DATE2021

Conference Paper

Conference proceedings

2021

Phase 1

EPI @ Supercomputing Frontiers Europe 2021

Jean-Marc Denis

Supercomputing Frontiers Europe

Presentation

2021

Phase 1

EPI @ OEHI 2021

EPI @ Teratec 2021

A RISC-V in-network accelerator for flexible high-performance low-power packet processing

Salvatore Di Girolamo

Thomas Benz

Timo Schneider

Torsten Hoefler

48th IEEE/ACM International Symposium on Computer Architecture (ISCA)

Conference Paper

2021

Phase 1

Server Microprocessor Market Forecast to Reach $18.1 Billion by 2026

Press coverage

2021

Phase 1

HPC Career Notes: August 2021 Edition

Press coverage

2021

Phase 1

Adoption of Council Regulation to Establish New EuroHPC Joint Undertaking

Press coverage

2021

Phase 1

Jean-Marc Denis Joins SiPearl as CSO

Press coverage

2021

Phase 1

BSC, Codeplay and SiFive help accelerate applications on RISC-V thanks to V-extension support in LLVM

Press coverage

2021

Phase 1

Amid a Canceled Tender, More Details of MareNostrum 5 (Finally) Emerge

Press coverage

2021

Phase 1

NVIDIA, Partners Extending Arm Ecosystem from Exascale to the Edge

Press coverage

2021

Phase 1

ISC21 Preview: EPI Chair Jean-Marc Denis Shares Vision for Future Supercomputers

Press coverage

2021

Phase 1

SiPearl Opens Site in Barcelona, its Second International Subsidiary

Press coverage

2021

Phase 1

SiPearl opens site in Barcelona

Press coverage

2021

Phase 1

Graphcore and SiPearl Form Strategic Partnership to Combine AI and HPC

Press coverage

2021

Phase 1

Cortus hopes to stake early RISC-V HPC claim

Press coverage

2021

Phase 1

EPI @ CARRV 2021

EPI @ ISCA 2021

ObserveNet Control: A Vision-Dynamics Learning Approach to Predictive Control in Autonomous Vehicles

IEEE Robotics and Automation Letters

Journal Article

2021

Phase 1

EPI @ RISC-V World Conference China

Roger Espasa

RISC-V World Conference China

Presentation

2021

Phase 1

EPI @ CPS&IoT Summer School

Benoît Dupont de Dinechin

Mario Kovač

CPS&IoT Summer School

Presentation

2021

Phase 1

Periodic Dissemination and Communication Report D24.3

OctoPath: An OcTree-Based Self-Supervised Learning Approach to Local Trajectory Planning for Mobile Robots

LVD-NMPC: A learning-based vision dynamics approach to nonlinear model predictive control for autonomous vehicles

EPI @ EuroCC and CASTIEL meeting

The Italian research on HPC key technologies across EuroHPC

Conference proceedings

2021

Phase 1

True Random Number Generator based on Fibonacci-Galois Ring Oscillators for FPGA

Press release: EPI EPAC1.0 RISC-V Test Chip Taped-out

FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Journal Article

2021

Phase 1

EPI @ IWOCL

EPI @ EuroHPC Summit Week 2021

EPI @ 2nd RISC-V Week

online, 2nd RISC-V Week

Presentation

2021

Phase 1

SiPearl launches the recruitment of 10 engineers per month in France & Germany

Press coverage

2021

Phase 1

Europe’s struggle to compete in the supercomputing arena, and why it needs to go from buyer to builder

Press coverage

2021

Phase 1

EPI @ DATE2021

Autoware Course Lecture 4: Platform HW, RTOS and DDS

Edge computing: Kalray webinar

Presentation

2020

Phase 1

Prometej Interview

EPI @ RIOS RISC-V Open Source Forum

EPI @ HPCC2020

EPI @ Open Source Summit

Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE

Neural Computing & Applications

Journal Article

2021

Phase 1

SEA-BREW: A scalable Attribute-Based Encryption revocable scheme for low-bitrate IoT wireless networks

Interview with Philippe Notton and Stéphane Requena

Press coverage

2021

Phase 1

EPI @ ApplePies

SiPearl Says Rhea Exascale Chip Has Entered Accelerated Simulation Phase for 2022 Launch

Press coverage

2021

Phase 1

EPI @ CASS Talks

EPI @ DVCon Europe 2020

EPI @ RISC-V Summit

Cross-level co-simulation and verification of an automatic transmission control on embedded processor

Conference proceedings

2021

Phase 1

Press release: EPI EPAC1.0 RISC-V core boots Linux on FPGA

SiPearl and Open-Silicon Research Collaborate to Accelerate Custom Silicon for HPC Applications

Press coverage

2021

Phase 1

Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities

Benoît Dupont de Dinechin

IEEE Signal Processing Magazine

Journal Article

2021

Phase 1

An Open-Source Scalable Thermal and Power Controller for HPC Processors

2020 IEEE 38th International Conference on Computer Design (ICCD)

Conference Paper

Conference proceedings

2020

Phase 1

EPI @ AI4People Summit 2020

Sergio Saponara

AI4People Summit 2020

Presentation

2020

Phase 1

EPI @ HPC Asia 2021

TSMC & Samsung Foundry Could Build Leading-Edge Fabs in Europe

Press coverage

2021

Phase 1

Performance Evaluation of Attribute-Based Encryption in Automotive Embedded Platform for Secure Software Over-The-Air Update

EPI at HiPEAC 2021

EPI @ HPC Connection Workshop, Supercomputing20

SiPearl Joins ETP4HPC to Help Drive Europe’s Sovereignty for HPC

Press coverage

2020

Phase 1

CEA Outlines Indigenous Path to European Exascale

Press coverage

2020

Phase 1

Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing

Embedded Image Processing the European Way: A new platform for the future automotive market

Conference proceedings

2020

Phase 1

SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative

EPI @ 20th PC Cluster Symposium

EU Member States Join Forces for a European Initiative on Processors, Semiconductor Technologies

Press coverage

2020

Phase 1

PhD Workshop on HW accelerators for AI and HPC

EPI @ IEEE Sensors France International Workshop 2020

Sergio Saponara

IEEE Sensors France Workshop

Presentation

2020

Phase 1

Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms

Conference proceedings

2020

Phase 1

EuroHPC Exec. Dir. Talks Procurement, EPI, and Europe’s Efforts to Control its HPC Destiny

Press coverage

2020

Phase 1

Press release: European Processor Initiative: Second year of activities

A Novel Posit-based Fast Approximation of ELU Activation Function for Deep Neural Networks

Conference proceedings

2020

Phase 1

EPI @ IEEE ICCD

EPI @ OEHI #2 Virtual Hackathon

Fabrizio Magugliani

CODES@OEHI virtual hackathon

2020

Phase 1

AI Computing for Automotive Powering Autonomy – Webcast Video

EPI @ Russian SC Days

EPI @ TAM

RISC-V is trying to launch an open-hardware revolution

Press coverage

2020

Phase 1

EPI @ RCML2020

EPI @ OpenFOAM

EPI @ ISSIP 2020

SiPearl Joins the Compute Express Link (CXL) Consortium

Press coverage

2020

Phase 1

EPI @ ASAP2020

Next TV Platform for Oct 9

Press coverage

2020

Phase 1

Reconfigurable Streaming Tensor Unit with Variable-Precision Posit Arithmetic

Conference proceedings

2020

Phase 1

Compiler-Assisted Data Streaming for Regular Code Structure

Nuno Neves

Nuno Roma

Pedro Tomás

IEEE Transactions on Computers

Journal Article

2020

Phase 1

EPI @ IEEE IMS Virtual Distinguished Lecture

Radio Free HPC: RISC-V Deep Dive, CTO Interview

Press coverage

2020

Phase 1

EPI @ FPL2020

European Commission proposes €8bn supercomputing investment

Press coverage

2020

Phase 1

EPI @ Linnaro Connect Virtual

Craig Prunty

Jean-Marc Denis

online, Linnaro Connect

Presentation

2020

Phase 1

EPI @ KSC20

EPI @ SMARTCOMP

EPI @ RISC-V Global Forum

Jean-Marc Denis

Roger Espasa

online, RISC-V Global Forum

Presentation

2020

Phase 1

European Commission Declares €8 Billion Investment in Supercomputing

Press coverage

2020

Phase 1

Digitale Souveränität bei Prozessoren

Press coverage

2020

Phase 1

EuroHPC Research and Innovation Call Announced

Press coverage

2020

Phase 1

New RISC-V CTO On Open Source Chip Architecture’s Global Data Center Momentum

Press coverage

2020

Phase 1

Next Platform TV for July 9

Press coverage

2020

Phase 1

EPI @ ACACES20

SiPearl, Arm to Present at the Open Innovation Platform Ecosystem Forum

Press coverage

2020

Phase 1

CODES@OEHI Hackathon 2019

Mirko Cestari

CODES@OEHI Hackathon 2019, Rome, Italy

Presentation

2019

Phase 1

EPI @ SemIsrael Virtual Tech Week 2020

Imen Baili

SemIsrael Virtual Tech Week 2020

Presentation

2020

Phase 1

EPI @ HPC CoE meeting

Dirk Pleiter

HPC CoE Meeting, online

Presentation

2020

Phase 1

How Europe Is Preparing Its Core Solution for Exascale Machines and a Global, Sovereign, Advanced Computing Platform

EPI @ ICS2020 online

Crypto-tile factsheet

Posits factsheet

Energy Efficiency in HPC @ IT4Innovations

Andrea Bartolini

IT4Innovations, Ostrava, Czech Republic

Presentation

2020

Phase 1

Fast deep neural networks for image processing using posits and ARM scalable vector extension

Journal of Real-Time Image Processing

Journal Article

2020

Phase 1

Frédéric Hannoyer Joins SiPearl as Chief Operating Officer

Press coverage

2020

Phase 1

SiPearl Appoints Craig Prunty as Vice President Marketing and Business Development

Press coverage

2020

Phase 1

EPI @ ESIWACE Virtual Workshop

Jesus Labarta

ESIWACE workshop, online

Presentation

2020

Phase 1

SiPearl to Open First International Operational Subsidiary in Germany

2020

Phase 1

SiPearl : le processeur européen sera un ARM plus puissant qu’un x86

Press coverage

2020

Phase 1

European Investment Advisory Hub Annual report 2019

Press coverage

2020

Phase 1

Arm technology to drive exascale supercomputer

Press coverage

2020

Phase 1

Mighty CPU rival to Intel and AMD set to shake up the market

Press coverage

2020

Phase 1

New Startup SiPearl Will Challenge AMD, Intel for Control of the EU HPC Market

Press coverage

2020

Phase 1

International CAE Conference

International CAE Conference, Vicenza, Italy

Flyer

2019

Phase 1

EPI @ IBM BarCamp No5

Jürgen Becker

IBM BarCamp, Böblingen, Germany

Presentation

2020

Phase 1

EPI @ AHPC2020

Philippe Notton

AHPC2020, Vienna, Austria

Presentation

2020

Phase 1

Undergraduate course: Electronic Industrial Systems Architecture and Programming Laboratory T-A

Huawei: Ubiquitous computing will usher in a new era of connected societies

Press coverage

2020

Phase 1

SiPearl – A New Contender For AMD and Intel Arrives

Press coverage

2020

Phase 1

European exascale project to leverage Arm’s Zeus platform

Press coverage

2020

Phase 1

Drilling down into the SiPearl European Arm Server Chip

Press coverage

2020

Phase 1

European Processor Initiative Backed SiPearl Announces Licensing of Arm Zeus Neoverse CPU IP

Press coverage

2020

Phase 1

Cryptographically Secure Pseudo-Random Number Generator IP-Core Based on SHA2 algorithm

A Fast Approximations of Activation Functions in Deep Neural Networks when using Posit Arithmetic

Philippe Notton: exclusive interview for AT

Press coverage

2020

Phase 1

EPI Talks podcast – EPIsode 1 – E4 and PCIe

Periodic Dissemination and Communication Report D24.2

Dissemination and Communication Plan D24.1

Bruxelles accorde une aide de 6,2 millions d’euros à SiPearl pour construire l’Europe des microprocesseurs

Press coverage

2020

Phase 1

EPI @ ESA Earth observation workshop

Mario Kovač

ESA EO Workshop, Zagreb, Croatia

Presentation

2020

Phase 1

EPI @ Forum FIC

FIC Forum, Lille, France

Flyer

2020

Phase 1

EPI @ Embedded World

Embedded World, Nürnberg, Germany

EPI @ OSS.5

OSS.5, San Francisco, USA

Flyer

2020

Phase 1

EPI @ 2nd R-CSS International Symposium

Jean-Marc Denis

R-CSS International Symposium, Kobe, Japan

Presentation

2020

Phase 1

Ying-Chih Yang Joins SiPearl as Chief Technical Officer

Press coverage

2020

Phase 1

SiPearl lève le voile sur les microprocesseurs du futur supercalculateur exascale européen

Press coverage

2020

Phase 1

Data Center Converged Hardware Is Just A Stop On The Road To A Universal Processor

Press coverage

2020

Phase 1

Europe’s Unified Strategy to Dominate the Global AI Market

Press coverage

2020

Phase 1

€6.2m for europrocessor

Press coverage

2020

Phase 1

EU pokrenula Inicijativu za Europski procesor za superračunala

Press coverage

2020

Phase 1

SiPearl Begins Development of European Processor with €6.2M

Press coverage

2020

Phase 1

EB’s contribution to world-class European high-performance computing and big data ecosystem

Press coverage

2020

Phase 1

Calista Redmond of the RISC-V: exclusive interview for AT

Press coverage

2020

Phase 1

Press release: First EPI Forum to take place in Paris

A PULP-based Parallel Power Controller for Future Exascale Systems

Conference proceedings

2020

Phase 1

The Floating Point Trinity: A Multi-modal Approach to Extreme Energy-Efficiency and Performance

Conference proceedings

2020

Phase 1

Crypto Accelerators for Power-Efficient and Real-Time on-Chip Implementation of Secure Algorithms

Conference proceedings

2020

Phase 1

Novel Arithmetics to Accelerate Machine Learning Classifiers in Autonomous Driving Applications

Conference proceedings

2020

Phase 1

Co-Design Factsheet

EPI Visual material

Exascale in Europe

Press coverage

2020

Phase 1

Le projet de processeur européen est toujours sur de bons rails

Press coverage

2020

Phase 1

Energy-efficient Computing Vital for Green Ambitions

Press coverage

2020

Phase 1

The European Union prepares its own prototype CPU

Press coverage

2020

Phase 1

European Processor Initiative Readies Prototype

Press coverage

2020

Phase 1

European Processor Initiative spins off SiPearl to commercialize the EPI microprocessor

Press coverage

2020

Phase 1

New Computing Architectures Needed to Achieve European Green Deal

Press coverage

2020

Phase 1

European SiPearl Startup designing microprocessor for Exascale

Press coverage

2020

Phase 1

SiPearl Joins EPI Consortium, Aims to Design Microprocessor for European Supercomputer

Press coverage

2020

Phase 1

The European Processor Initiative Gets Ready for Commercialization with Startup SiPearl

Press coverage

2020

Phase 1

The Strength of Europe’s Homegrown Innovation

Press coverage

2019

Phase 1

Silicon is hot in Silicon Valley again

Press coverage

2019

Phase 1

EPI: EuroHPC Industrial Cornerstone

Jean-Marc Denis

SOS23 Workshop, Asheville, NC, USA

Presentation

2019

Phase 1

EPI @ HiPEAC conference in Bologna

HiPEAC conference, Bologna, Italy

IEEE – BEE Week 2019

Sergio Saponara

IEEE, Bordeaux, France

Presentation

2019

Phase 1

EPI All Factsheets Package

eFPGA – embedded FPGA factsheet

E4 at the IBM AI Bologna – Anomaly detection in Finance & AutoAI

Fabrizio Magugliani

IBM AI Bologna, Bologna, Italy

Presentation

2019

Phase 1

STX – stencil/tensor accelerator factsheet

MPPA automotive accelerator factsheet

EPI VaRiable Precision Processor factsheet

EPI Automotive factsheet

EC Workshop on Open Source Software and Hardware

Jesus Labarta

EC workshop on Open Source, Brussels, Belgium

Presentation

2019

Phase 1

EPI poster @ Ph.D. Workshop on Next-Generation Cloud Infrastructure at Microsoft Research, Cambridge

Enrico Reggiani

Fabio Banchelli

Filippo Mantovani

MSR Cambridge lab, Cambridge, UK

Poster

2019

Phase 1

EPI partner @ Numerical combustion

Numerical combustion, Aachen, Germany

Flyer

2019

Phase 1

A clarifying look at the ETP4HPC role in EuroHPC and opportunities for European SMEs

Press coverage

2019

Phase 1

Server Microprocessor Markets – Worldwide Insights & Forecasts to 2024

Press coverage

2019

Phase 1

European Cyber Week: EPI Embedded Security

Dominique Bolignano

European Cyber Week, Rennes, France

Presentation

2019

Phase 1

EPI @ SemIsrael Expo

SemIsrael Expo, Tel Aviv, Israel

Flyer

2019

Phase 1

EPI @ EFECS

EFECS, Helsinki, Finland

EPI @ Supercomputing19

Dirk Pleiter

Jean-Marc Denis

Ying-Chih Yang

SC19, Denver, Colorado, USA

Peak performance: Francesco Morsiani

Press coverage

2019

Phase 1

EPI partners @ HiPEAC CSW

EPI flyer @ Arm TechCon

San Jose, California, USA

Flyer

2019

Phase 1

IDCS2019: When performance matters

Fabrizio Magugliani

IDCS2019, Napoli, Italy

Presentation

2019

Phase 1

75 HPC User forum: EPI

Jean-Marc Denis

HPC User Forum, Edinburgh, Scotland

Presentation

2019

Phase 1

74 HPC User forum: EPI

Jean-Marc Denis

HPC User Forum, Lugano, Switzerland

Presentation

2019

Phase 1

DEIB@Politecnico di Milano: Edge Comupting: For when the cloud it too far away

Fabrizio Magugliani

DEIB@Politecnico di Milano, Milano, Italy

Presentation

2019

Phase 1

EPI flyer @ AutoSens

AutoSens, Brussels, Belgium

Flyer

2019

Phase 1

EPI Consortium members list

EPI Backgrounder

EPI Quote sheet

EPI Factsheet General

Barcelona impulsará el diseño de un procesador de supercomputación europeo

The duty of digital sovereignty – Senat

EPI to develop Common Platform for general purpose microprocessor and accelerators for exascale machines and automotive industry

Press release: European Processor Initiative: First year of activities

The RISC-V Week: First steps towards a made-in-Europe processor

Denis Dutoit

Romain Dolbeau

RISC-V Week, Paris, France

Presentation

2019

Phase 1

Europeans Add 3D Integration to Exascale Technology Stack

Continental workshop – automotive showcase

Sergio Saponara

Continental workshop, Pisa, Italy

Presentation

2019

Phase 1

Tongji University – Automotive Summit

Jürgen Becker

Automotive summit, Tongji University, Shanghai, China

Presentation

2019

Phase 1

Changing Approaches to HPC systems

Mario Kovač

Publication - magazine

2018

Phase 1

Made in Europe: Taking a major step towards building supercomputers

Press coverage

2019

Phase 1

IEEE I&M Chapter/GDR SoC2 Workshop

Sergio Saponara

IEEE I&M Chapter, Nancy, France

Presentation

2019

Phase 1

Arm Research Summit – FFTW3: Leveraging the SVE

Romain Dolbeau

Ying-Chih Yang

Arm Research Summit, Austin, Texas, USA

Presentation

2019

Phase 1

EPI flyer @ TSMC OIP Forum USA

TSMC OIP, Santa Clara, USA

Flyer

2019

Phase 1

ParCo – EPI: the European vision for exascale ages and beyond

Jean-Marc Denis

ParCo, Prague, the Czech Republic

Presentation

2019

Phase 1

ApplePies – Round Table

ApplePies, Pisa, Italy

HPC User Forum Chicago

Jean-Marc Denis

HPC User Forum, Chicago, USA

Presentation

2019

Phase 1

ITWSHPC Workshop

Andrea Bartolini

ITWSHPC Workshop, Bologna, Italy

Presentation

2019

Phase 1

IEEE CASS Seasonal School – IoT for Automotive Industry: New Trends in Circuits and Systems

Sergio Saponara

IEEE CASS, Porto Alegre, Brazil

Presentation

2019

Phase 1

EPI @ Flash Memory Summit

FMS, Santa Clara, USA

Flyer

2019

Phase 1

Livorno Pierburg Rheinmetall plant workshop

Sergio Saponara

Pierburg Rheinmetall plant, Livorno, Italy

Presentation

2019

Phase 1

ET-I2oT 2019 – Embedded High Performance Computing: the challenge of the H2020 EPI

Sergio Saponara

ET-I2oT 2019, Pisa, Italy

Presentation

2019

Phase 1

HiPEAC ACACES 2019 – The strategic touch between supercomputers and embedded systems in the roadmap towards exascale: EPI

Mauro Olivieri

HiPEAC ACACES 2019, Fiuggi, Italy

Presentation

2019

Phase 1

NEWCAS 2019 – Kalray’s MPPA® Manycore Processor: At the Heart of Intelligent Systems

Benoît Dupont de Dinechin

IEEE NEWCAS, Munich, Germany

Presentation

2019

Phase 1

Press release: First steps towards a-made-in-Europe high-performance microprocessor

InSiDE Magazine – EPI builds in-Europe processor technologies

Dirk Pleiter

Estela Suarez

https://www.gauss-centre.eu/news/publications/inside/

Publication - magazine

2019

Phase 1

SIA CESA 5.0 – European Processor Initiative

Philippe Notton

SIA CESA 5.0, Versailles, France

Presentation

2018

Phase 1

RES User – The future MareNostrum 5 and EPI

Mateo Valero

RES User conference, Zaragoza, Spain

Presentation

2019

Phase 1

An Update on the European Processor Initiative

Press coverage

2019

Phase 1

“J’ai trouvé des pépites ! Beaucoup de pépites” (Emmanuel Chiva, Agence Innovation Défense)

Press coverage

2019

Phase 1

The European Processor Initiative’s Ambitious Vision of the Future

Press coverage

2019

Phase 1

EPI tutorial – HPC Processor landscape

EPI first tutorial, Barcelona, Spain

EPI tutorial – Automotive

Francisco J. Cazorla

Jaume Abella

EPI first tutorial, Barcelona, Spain

EPI tutorial – Accelerator

Mauro Olivieri

EPI first tutorial, Barcelona, Spain

EPI tutorial – Software

Jesus Labarta

EPI first tutorial, Barcelona, Spain

How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing

Un chip europeo para la soberanía tecnológica

Press coverage

2019

Phase 1

RISC-V: Rhea el primer chip europeo y primer fruto de EPI

Press coverage

2019

Phase 1

Europe will enter pre Exascale realm with Marenostrum 5

Press coverage

2019

Phase 1

L’UE développe son propre processeur pour atteindre l’Exascale

Press coverage

2019

Phase 1

Nvidia Embraces Arm, Declares Intent to Accelerate All CPU Architectures

Press coverage

2019

Phase 1

Europe’s homegrown HPC computer begins to take shape

Press coverage

2019

Phase 1

Supercalcul : L’Europe passe à l’offensive

Press coverage

2019

Phase 1

Maintaining Europe’s edge in supercomputing software

Press coverage

2019

Phase 1

EPI Rollup 1

EPI Poster 2

EPI Poster 1

The race to exascale: A story of superpowers and supercomputers

Press coverage

2019

Phase 1

EPI Flyer 1 Outside

EPI Flyer 1 Inside

Chapter in Electronic Components and Systems for Automotive Applications

Conference proceedings

2019

Phase 1

RISC-V Workshop – Energy efficient computing from Exascale to MicroWatts: The RISC-V playground

Luca Benini

RISC-V workshop, Zurich, Switzerland

Presentation

2019

Phase 1

EPI @ ISC 2019 Exhibition

EPI

Philippe Notton

ISC2019, Frankfurt, Germany

HiPEACinfo57 – Homegrown high performance: The European Processor Initiative

Mario Kovač

HiPEACinfo57

Publication - magazine

2019

Phase 1

FEDfRo’2019 – EPI processor and its robustness requirements

Ying-Chih Yang

FEDfRo'2019, Rhodes Island, Greece

Presentation

2019

Phase 1

WOSH – EPI and beyond: perspectives of a European supercomputing center on open-source hardware and software

Mauro Olivieri

WOSH, Zurich, Switzerland

Presentation

2019

Phase 1

WOSH – EPI: The Industrial cornerstone of EuroHPC for Exascale Era

Mario Kovač

WOSH, Zurich, Switzerland

Presentation

2019

Phase 1

Teratec – Electric/electronic architecture as an enabler for connected mobility and automated driving

Matthias Traub

Teratec Forum, Palaiseau, France

Presentation

2019

Phase 1

EPI as an enabling technology for smart vehicles and mobility

Sergio Saponara

ICT Innovation on Vehicular Technology and Applications workshop, Pisa, Italy

Presentation

2019

Phase 1

CRIANN – EPI: a High Performance, High Efficiency Processor for HPC

Romain Dolbeau

Journée scientifique 2019 du Criann, Rouen, France

Presentation

2019

Phase 1

EPI flyer @ Design Automation Conference

DAC, Las Vegas, Nevada, USA

Flyer

2019

Phase 1

IHPCF – From EPI to ExaScale

Ying-Chih Yang

The 4th International High Performance Computing Forum, Chengdu, China

Presentation

2019

Phase 1

EuroHPC Summit Week

Mateo Valero

EuroHPC Summit Week, Poznan, Poland

Computing Frontiers – EPI: The Industrial Cornerstone of EuroHPC for Exascale Era

Mario Kovač

International Conference on Computing Frontiers 2019, Alghero, Sardinia, Italy

Presentation

2019

Phase 1

5G and Tomorrow – EPI: embedded High Performance Computing for Automated and Connected Vehicles

Sergio Saponara

National conference on 5G and the Mobility of Tomorrow, Pisa, Italy

Presentation

2019

Phase 1

ISS – BSC Roadmap for HPC in Europe

Mateo Valero

Industry Strategy Symposium, Milano, Italy

Presentation

2019

Phase 1

HPCXXL User Group – EPI: The EuroHPC Industrial Cornerstone

Mario Kovač

Winter meeting, Swiss conference & HPCXXL User Group, Lugano, Switzerland

Presentation

2019

Phase 1

EPI Poster @ DATE Conference and Exhibition

DATE, Florence, Italy

Poster

2019

Phase 1

EPI Teaser @ SC Asia

MWC 2019 – Mobiles: on the road to Supercomputers

Mateo Valero

GoingDigital Community, Barcelona, Spain

Presentation

2019

Phase 1

RIKEN – Europe strikes back

Ying-Chih Yang

1st R-CCS International Symposium, Kobe, Japan

Presentation

2019

Phase 1

CIC Mexico invited talk – HPC Perspectives and Challenges for Europe

Mateo Valero

Centro de Investigación en Computación del IPN, Ciudad de Mexico, Mexico

Presentation

2019

Phase 1

ICT Event 2018 – HPC Perspectives and Challenges for Europe

Mateo Valero

ICT Event - Imagine Digital - Connect Europe, Vienna, Austria

Presentation

2018

Phase 1

Smarter memory paves the way for EU independence in computer manufacturing

EPI at HIPEAC25

European AI ecosystem worried about new US export restrictions

Most Significant Digit First Multiply-and-Accumulate Unit for Neural Networks

RTL Flow for the Power Side-Channel Resilience Assessment of a Post-Quantum SHA-3 Accelerator

On hardware acceleration of quantum-resistant FOTA systems in automotive

Data Prefetching on Processors with Heterogeneous Memory

Exploiting Vector Code Semantics for Efficient Data Cache Prefetching

Graph Computing on Long Vector Architectures (Yes, It Works!)

HW-SW Interface Design and Implementation for Error Logging and Reporting for RAS Improvement

Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures

CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms

A PUF-Based Secure Boot for RISC-V Architectures

Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative

NDPmulator: Enabling Full-System Simulation for Near-Data Accelerators From Caches to DRAM

Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments

gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation

Decoding-free Two-Input Arithmetic for Low-Precision Real Numbers

Hardware Design of an Advanced-Feature Cryptographic Tile within the European Processor Initiative

Review of Methodologies and Metrics for Assessing the Quality of Random Number Generators

At the EPI forum in Barcelona eeNews Europe discussed the state of the initiative with Eric Monchalin, the chair of the European Processor Initiative

ARM and RISC-V are at the helm of the European Processor Initiative

The European Processor Initiative aims to bring together research, design and manufacturing of a home-grown European processor

EPI Forum in Barcelona

Press release: EPI Forum in Barcelona, October 9-10, Barcelo Sants hotel

AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads

ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration

A High-Performance, Energy-Efficient Modular DMA Engine Architecture

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation

Trading Performance, Power, and Area on Low-Precision Posit MAC Units for CNN Training

Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation

Sparse Matrix-Vector Multiplication Based on Online Arithmetic

Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor

OpenHW CORE-V High-Performance, Out-of-Order, L1 Data Cache (HPDCache)

What We Know about Alice Recoque, Europe’s Second Exascale System

Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V

Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency

COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores

Software Development Vehicles to Enable Extended and Early Co-design: A RISC-V and HPC Case of Study

Supporting RISC-V Performance Counters Through Linux Performance Analysis Tools

A Hardware-Centric Approach to Increase and Prune Regular Activation Sparsity in CNNs

$400m RISC-V design centre for Barcelona

Hewlett Packard Enterprise and SiPearl Partner to Develop HPC Solutions with European Processors and Accelerate Europe’s Adoption of Exascale Supercomputers

Indigenous HPC: What It Means and Why Now

Joined up thinking: Europe to oversee trio of projects for homegrown chips, HPC gear

EuroHPC Launches 3 New Research and Innovation Projects

E4 Contributes to the Success of the European Processor Initiative

E4 helps EPI in chip and HPC independence

French cybersecurity firm ProvenRun gets €15M from Tikehau Capital, others for IoT security advancements

European Processor Initiative (EPI) partner SiPearl will provide its general purpose processor for Europe’s first EuroHPC exascale supercomputer JUPITER

Održan Dan Hrvatskog centra kompetencija za HPC

European Processor Initiative achieves significant sovereignty contribution

European Processor Initiative Drives Digital Sovereignty Forward with JUPITER

The EPAC1.5 – a significant milestone in high-performance computing

The EPAC1.5 – a significant milestone in high-performance computing

European Processor Initiative partner SiPearl will provide its general purpose processor for Europe’s first EuroHPC exascale supercomputer JUPITER

Why Europe must have a home-grown HPC processor

Europe’s first exascale supercomputer will use Arm processors with Nvidia GPU nodes

The European Union announces Jupiter, its first supercomputer that exceeds exaFLOP power

European high performance processor designer SiPearl has won its first major customer in JUPITER, the European exascale supercomputer to be built in Germany

EU Unveils Its First ExaFlop Supercomputer, Featuring The Power Of ARM & NVIDIA

JUPITER Exascale Supercomputer, lead customer for SiPearl

Europe’s exascale supercomputer in its starting blocks

Jupiter exascale supercomputer to be built by Atos’ Eviden

An Eviden led consortium to build Europe’s first exascale supercomputer

EU Grabs ARM for First ExaFLOP Supercomputer, x86 Misses Out

EuroHPC Amplifies European Research and Industry with JUPITER’s Exascale Potential

HPC: Enabling Science at Scale

An open source cloud software ecosystem for the EPI hardware

The Golden Age of Custom Silicon Draws Near: Part 2

ACM Europe Summer School on HPC Computer Architectures for AI and Dedicated Applications

Configurable 64-bit RISC-V IP Targets Machine Learning, Other Advanced Apps

RISC-V CPUs: Enabling Processor Innovation

Vivian Blanchard Named VP Hardware R&D at SiPearl

EuroHPC Executive Director Talks Europe’s Supercomputing Future

Semidynamics launches world’s first fully customisable RISC-V IP cores

SiPearl raises €90m for Rhea European supercomputer chip

SiPearl Raises $98.3M in Series A Funding to Launch Rhea HPC Microprocessor

SiPearl Raises $98.3M in Series A Funding to Launch Rhea HPC Microprocessor