At the EPI forum in Barcelona eeNews Europe discussed the state of the initiative with Eric Monchalin, the chair of the European processor initiative
ARM and RISC-V are at the helm of the European Processor Initiative
The European Processor Initiative aims to bring together research, design and manufacturing of a home-grown European processor
EPI held its first EPI forum in Barcelona, on October 9 and 10, 2024. It was a two-day event with the following presentations:
- Etienne Walter (Eviden, an Atos business): EPI Overview
- Stephane Requena (GENCI): AI Keynote
- Mateo Valero (BSC): European Supercomputers Keynote: Buy versus Build
- Jean-Pierre Panziera (Eviden, an Atos business): High Performance Computing in the AI era
- Eric Lalardie (Arm): Enabling European Innovation with Arm Technology
- Daniele Piccarozzi (AMD): AMD solutions for HPC and AI
- Philippe Notton (SiPearl): Overview of SiPearl’s Seine Platform
- Roger Espasa (SMD): Semidynamics All-in-One solution for next-generation RISC-V AI
- Craig Prunty (SiPearl): Arm/Rhea in high-end HPC
- Alexandra Kourfali (EuroHPC JU): EuroHPC chips initiatives: the road towards European technological sovereignty
- Rod Evans (NVIDIA): Enabling AI Nations
- Filippo Mantovani (BSC): Pushing RISC-V to HPC: the story of EPI Accelerator (EPAC)
- Filippo Mantovani (BSC): VEC
- Andrea Bocco (CEA): VRP
- Tim Fischer (ETHZ): STX
- David Snelling (Fujitsu): Fujitsu-Monaka: Data Center Ready, ARM Processor
The presentations are available in the zip file of this item.
Project press release, published on September 5th, 2024, is also available in the news section: https://www.european-processor-initiative.eu/epi-forum-in-barcelona-october-9-10-barcelo-sants-hotel/
EPI Consortium members published “ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation” in the International Journal of Parallel Programming.
Here you can find a link to an open access version of the article: https://www.research-collection.ethz.ch/handle/20.500.11850/663701
DOI: 10.1007/s10766-024-00761-4
EPI Consortium members published “Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation” in the IEEE Transactions on Computers.
EPI Consortium members published “Sparse Matrix-Vector Multiplication Based on Online Arithmetic” in the IEEE Access.
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