Oumaima Matoussi from CEA presented the paper titled “NoC Performance Model for Efficient Network Latency Estimation”.

Here is the presentation from the conference. OA link for the paper is here: https://hal.archives-ouvertes.fr/hal-03207778.

Ideja je vječna – HPC topic at Croatian Radiotelevision

Peter Hsu from BSC participated in the RIOS Lab RISC-V event with a talk titled RISC-V at Barcelona Supercomputing Center.

EPI Consortium members published “Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE” in Neural Computing & Applications.

Here you can find a link to an open access version of the article:

https://link.springer.com/article/10.1007/s00521-021-05814-0

DOI: https://doi.org/10.1007/s00521-021-05814-0

EPI Consortium members published “SEA-BREW: A scalable Attribute-Based Encryption revocable scheme for low-bitrate IoT wireless networks” in the Journal of Information Security and Applications.

Here you can find a link to an open access version of the article:

https://arxiv.org/abs/2101.10008

DOI: https://doi.org/10.1016/j.jisa.2020.102692

Interview with Philippe Notton and Stéphane Requena

SiPearl Says Rhea Exascale Chip Has Entered Accelerated Simulation Phase for 2022 Launch

EPI Consortium members published “Cross-level co-simulation and verification of an automatic transmission control on embedded processor” in the Software Engineering and Formal Methods. SEFM2020 Collocated Workshops.

Here you can find a link to an open access version of the article:

https://arpi.unipi.it/retrieve/handle/11568/1082839/692127/CoSim-CPS2020.pdf

DOI: https://doi.org/10.1007/978-3-030-67220-1_20

Project press release, published on March 9, 2021, is also available in the news section:
https://www.european-processor-initiative.eu/epi-epac1-0-risc-v-core-boots-linux-on-fpga/

SiPearl and Open-Silicon Research Collaborate to Accelerate Custom Silicon for HPC Applications