Home Dissemination Communication Press Repository Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures

Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures

EPI Consortium members published “Design and Evaluation of a Peripheral for Integrity Checking to Improve RAS in RISC-V Architectures” at SEEDA-CECNSM.

Here you can find a link to an open access version of the article: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10470707.

DOI: https://doi.org./10.1109/SEEDA-CECNSM61561.2023.10470707

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Publication Type: Conference Paper
Year of Publication:
Authors: Authors listed in alphabetical order: - Daniele Rossi - Nicasio Canino - Sergio Saponara - Stefano Di Matteo - Vasileios Tenentes
Publisher: IEEE
Name of publication/Event: SEEDA-CECNSM
ISSN Number:
Keywords:
URL: https://doi.org./10.1109/SEEDA-CECNSM61561.2023.10470707

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This project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

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