Home Dissemination Communication Press Repository A RISC-V in-network accelerator for flexible high-performance low-power packet processing

A RISC-V in-network accelerator for flexible high-performance low-power packet processing

EPI Consortium members published “A RISC-V in-network accelerator for flexible high-performance low-power packet processing” in 48th IEEE/ACM International Symposium on Computer Architecture (ISCA).

Here you can find a link to an open access version of the article: https://ieeexplore.ieee.org/document/9499874.

DOI: https://doi.org/10.1109/ISCA52012.2021.00079.

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Publication Type: Conference Paper
Year of Publication: 2021
Authors: Alexandru Calotoiu - Andreas Kurth - Jakub Beránek - Luca Benini - Salvatore Di Girolamo - Thomas Benz - Timo Schneider - Torsten Hoefler
Publisher: IEEE
Name of publication/Event: 48th IEEE/ACM International Symposium on Computer Architecture (ISCA)
ISSN Number: 2575-713X
Keywords: RISC-V
URL: https://ieeexplore.ieee.org/document/9499874

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This project has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 and Specific Grant Agreement No 101036168 (EPI SGA2). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland.

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