Impressions from the EuroHPC Summit Week 2019, that was held from 13 to 17 May in Poznań, Poland, are still fresh, as the event turned out a huge number of attendees and interesting topics covered in the 4-day event.
European Processing Initiative, under the moderating lead of Mr Leonardo Flores Añover and Mr Andrea Feltrin from DG CNECT, participated in a half-day workshop titled “Co‐designing with the European Processor Initiative”. The goals of the workshop were to identify applications that could drive co‐design for EPI and the pilot system projects; introduce attendees to co‐design for EPI and pilot system ideas leading to supercomputers based on EPI technologies; discuss component‐level vs. system‐level co‐design: who does what when; highlight ongoing co‐design efforts within EPI; bring application and technology/system architecture experts together; show the current status of the software landscape, and discuss how they can contribute to a coherent effort towards the European Exascale supercomputers.
Presenters from EPI covered those topics in 6 short presentations, while the session closed with an expert panel. Participants of the panel emphasized the importance of selecting a set of communities and involving them strongly in the co-design process. The communities should be those that really need Exascale performance, have high societal impact and are committed to participate in the co-design work. The systems in question will be heterogeneous and it is important to make them as user-friendly as possible; therefore, the middleware and programming environment play a very important role.
The panel also concluded that the use of HPC systems as workflows is increasing – they very often contain HPC with HPDA and AI. At Exascale level, workflows add an order of magnitude to the complexity. Using the sole general purpose processor combined at interposer level with many different accelerators helps drive the complexity down. EPI offers this unique feature. It is very important to provide middleware to properly support for workflows, also on heterogeneous systems.
The pilot system must demonstrate scalability, energy efficiency and reliability. Risks should be limited to a particular aspect/component of the system and the pilots should be operational, enable application running on them to prepare for Exascale, and provide results that increase visibility. The panel believes such visibility can be ensured through training as well – it is an opportunity to attract more people to the HPC field. It should be more attractive for young people, starting as early as school level. The panel concluded, looking to the future developments, that after Exascale, the goal should be not so much related to increasing speed, but making the Exascale systems much more efficient. Real-world application and workflow efficiency, as well as performance, need to be increased.
Prof. Mateo Valero, director of the Barcelona Supercomputing Center, presented the European Processor Initiative in RISC-V Workshop, Barcelona 7-10 May, 2018. His keynote focused on the role of RISC-V architecture in the EPI project and in future exascale computing systems in general.
Consortium partners of the European Processor Initiative (EPI) met in Brussels on December 18th and 19th 2018 to kick off the project that will be the cornerstone of EU’s strategic plans in High-Performance Computing.
The Initiative gathers 26 partners from 10 European countries with the aim of bringing to the market a low-power microprocessor and ensuring that the key competence of high-end chip design remains in Europe. The European Union’s Horizon 2020 program funded this new project with a special Framework Partnership Agreement. The initial stage is a three-year Special Grant Agreement 1, that is expected to finish in November 2021.
Experts gathered in EPI cover all the relevant areas for such a feat: High-Performance Computing research community, major supercomputing centres, and the computing, automotive and silicon industry as well as the potential scientific and industrial users. Through a co-design approach, it will design and develop the first European HPC System on Chip and accelerators through several major streams of operation:
- Common Platform and global architecture stream
- HPC general purpose processor stream
- Accelerator stream
- Automotive platform stream
The consortium agreed on the objectives of the kick-off which were to agree on the project management control, provide information on the technical development, define syncing points between tasks and ensure all stream leaders and Global Technical Leader have enough information to proceed with the projects schedule. On the first day, the partners discussed management and dissemination and communication activities, as well as global technical stream, in addition to a General Assembly meeting, while the second day was reserved for parallel sessions on specific streams.
Philippe Notton, General Manager of the European Processor Initiative, gave a presentation on EPI activities and efforts in Lisbon, November 21st 2018, attending the European Forum for Electronic Components and Systems. Presenting EPI goals, Mr Notton explained the core ideas behind EPI project and its overall line-up with European strategic goals set out in EuroHPC JU. He also presented the EPI Roadmap, ranging from 2021 towards the vision in 2024 – from Generation 1 General-purpose Processor, through Generation 2 and Generation 3, utilizing EPI common platform
The European Commission published an official announcement of the European Processor Initiative (EPI) on its website. The announcement confirmed there are 23 partners in the project and the budget amounts to 120 million euro.
Take a look at the EC announcement
Article written by prof. dr. sc. Mario Kovač, Dissemination Leader of the European Processor Initiative, has been published on CIO Applications Europe.
The article introduces EPI’s goals and efforts in tackling global challenges and potential European responses to HPC-related activities.
Read the whole article about “Changing Approaches to HPC Systems
Philippe Notton, General Manager of the European Processor Initiative, gave a presentation on EPI activities and efforts in Versailles, December 5th2018, attending the SIA CESA 5.0 International Conference and Exhibition.
Presenting EPI goals, Mr Notton explained the core ideas behind EPI project and its overall line-up with European strategic goals set out in EuroHPC JU. He also presented the EPI Roadmap, ranging from 2021 towards the vision in 2024 – from Generation 1 General-purpose Processor, through Generation 2 and Generation 3, utilizing EPI common platform.
Jean-Marc Denis, Chairman of the Board of the European Processor Initiative, attended the Supercomputing Asia event in Singapore, at the Suntec Singapore Convention and Exhibition Centre, presenting EPI activities and efforts.
Visitors to SC Asia could also find out more about EPI’s goals and roadmap by visiting the European Commission booth, which graciously hosted EPI materials, flyers and posters. Pictured here is Sébastien Varrette, from the Université du Luxembourg, at the EC/EPI/PRACE booth.
