The 2024 edition of the ACM Summer School on HPC Architectures for AI and Dedicated Applications, organized by The Barcelona Supercomputing Center (BSC) and the Universitat Politècnica de Catalunya (UPC), will take place in Barcelona from 2-6 September 2024. This year’s program focuses on the convergence between HPC and AI, and it will also explore emerging research areas such as Quantum Computing. The school targets PhD and recent postdocs in HPC and AI. Exceptionally, outstanding MSc students with proven interest and/or experience in projects related to HPC and/or AI are also accepted. Participation in the school is free of charge. Sixty accepted participants will spend one week in Barcelona, attending formal lectures, invited talks, and other activities. The school will cover accommodation expenses and catering during school hours.
More information: https://europe.acm.org/seasonal-schools/hpc/2024
For another year, the entire European and global HPC community gathered to attend the ISC24 in Hamburg, Germany, seeing that it is likely the biggest and most important European HPC conference.
The theme was “Reinventing HPC into ISC 2024” and it was attended by more than 3,400 people in the Exhibition part, with more than 160 exhibitors at their respective booths.
The European Processor Initiative co-hosted a booth together with our colleagues from EUPEX and EUPILOT projects, where our tireless researchers and staff answered numerous questions about the activities in our project.
Colleagues from Barcelona Supercomputing Center, Filippo Mantovani and Fabio Banchelli Garcia, performed an EPAC prototype demo with a RISC-V vector processing unit, which garnered a lot of interest from participants.
On Wednesday, representatives from all three projects co-organized a Birds of Feather session called “European Processor Initiative & the Pre-Exascale Pilots”. The speakers were Pascale Bernier-Bruna (Eviden), Etienne Walter (Eviden), Carlos Puchol (BSC), and the session was moderated by Romana Konjevod (BSC). All three projects presented their goals in a short slide deck, and then opened the floor to a Q/A session. The BoF session had a full house, with many interested ISC attendees coming to participate in the discussion.
Collaboration among European research initiatives is crucial for the optimization of novel technologies and optimization of software. Thanks to the participation of Barcelona Supercomputing Center (BSC) and Polytechnic University of Valencia (UPV) researchers in the European eFlows4HPC and EPI projects, they developed optimised kernels for machine and deep learning (DL) operators that can replace the compute-intensive simulations in application workflows. EPI has provided a set of hardware/software tools for testing EPAC-VEC demonstrating that this technology can significantly accelerate the performance of the convolution.
After three years of research, the European project eFlows4HPC came to its end in February 2024. One of its target architectures was to investigate the benefits of novel computer architectures, such as the ones from EPI. eFlows4HPC experts optimized kernels for specific heterogeneous architectures. In particular, they optimised kernels on ARM-based architectures, equipped with “narrow” SIMD arithmetic units (single instruction, multiple data) arithmetic units, and RISC-V architectures, equipped with long vector processing units such as the one proposed in EPI, putting a strong emphasis on portability.
In addition, BSC and UPV experts migrated some of the computational kernels in the eFlows4HPC workflows to the EPI. eflows4HPC experts tested SVD on EPI hardware obtaining a clear the reduction of execution time from using the VPU (vector version of the routines) compared with an execution only using the RISC-V core (scalar version).
One of the eFlows4HPC Key Exploitable results (KER) is Convolution operators on multicore ARM and RISC-V architectures (CONVLIB), fully developed by UPV. CONVLIB is a library containing high performance implementations of convolution algorithms for multicore platforms with ARM and RISC-V architectures. It contains a driver routine that identifies the best values for four hyper-parameters: micro-kernel, cache configuration parameters, parallelization loop and algorithm, automatically adapting the call to the dimensions of the convolution operator. At EPAC-VEC level, UPV researchers in collaboration with BSC experts migrated ConvLIB to exploit the VPU accelerator in this architecture showing that the EPAC-VEC can significantly accelerate the performance of the convolution. “These experiments show that the EPAC-VEC can significantly accelerate the performance of the convolution, but it does require a very careful implementation of the codes”, states Enrique S. Quintana, UPV professor and eFlows4HPC work package leader. This library is now available at the open software repository here: https://github.com/hpca-uji/ConvLIB
The results of this research have also been published in the following peer-reviews publication:
Ramírez, A., Castelló, and E. S. Quintana-Ortí, “A BLIS-like matrix multiplication for machine learning in the RISC-V ISA-based GAP8 processor,” J. of Supercomputing, 2022. https://doi.org/10.1007/s11227-022-04581-6.
About eFlows4HPC
eFlows4HPC is a European-funded project with a budget of €7.6M that started on 1 January 2021 and lasted 3 years and 2 months. Coordinated by BSC (Spain), the project brings together a multidisciplinary consortium: CIMNE (Spain), FZJ (Germany), UPV (Spain), ATOS (France), DtoK Lab (Italy), CMCC (Italy), INRIA (France), SISSA (Italy), PSNC (Poland), UMA (Spain), AWI (Germany), INGV (Italy), ETHZ (Switzerland), Siemens (Germany), and NGI (Norway).
The eFlows4HPC project has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 955558. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Spain, Germany, France, Italy, Poland, Switzerland, Norway. It also received funding from MCIN/AEI/10.13039/501100011033 and the European Union NextGenerationEU/PRTR (PCI2021-121957).
EuroHPC Summit 24, a conference gathering European key stakeholders and users in the high-performance computing field, was held from March 18 to March 21, 2024, in Antwerp, Belgium.
The conference gathered more attendees than ever before, who were eager to see that is new in the European HPC space and perhaps eager to visit poster sessions, demos or finally, get a special look into the work of European supercomputers.
The European Processor Initiative was present at the event. Our CCO, Mario Kovač, attended the poster sessions explaining how far along we are in the project timeline.
Colleagues from Barcelona Supercomputing Centre showcased the EPAC chip, the first RISC-V based prototype leveraging vector acceleration coming from the EPI project.
EPI’s General Manager, Etienne Walter, and SiPearl’s CEO and founder, Philippe Notton, attended the parallel sessions on European Chip Initiatives for HPC, where they gave a detailed overview of what EPI is doing right now and what kind of developments can be underway for Rhea1 and Rhea2 processors.
On July 19th, the Council Regulation establishing the European High-Performance Computing Joint Undertaking was published in the Official Journal of the European Union. It was formally adopted on July 13th, by the Economic and Financial Affairs Council.
This is an important piece of news for the HPC community, opening up EuroHPC JU’s ability to draw funds from the Horizon Europe, Digital Europe and the Connecting Europe Facility programmes. The news item and full regulation text can be found on the EuroHPC JU’s website, here:
Taking place on 30 August – 3 September 2021, the second ACM Europe Summer School on HPC Computer Architectures for AI and Dedicated Applications will be co-hosted by Barcelona Supercomputing Center (BSC), in conjunction with the Universitat Politècnica de Catalunya – Barcelona Tech (UPC).
The programme of this year’s summer school, which will be fully remote, centres around topics within the European Processor Initiative. Open hardware expert Luca Benini (ETH Zürich / University of Bologna) will be discussing machine learning from a RISC-V platform perspective, while the EPI Accelerator stream leader Jesús Labarta (BSC) will train attendees in performance analysis and hybrid programming, helping them get the very best out of their code. Meanwhile, Mauro Olivieri (Sapienza – University of Rome / BSC) will present vector acceleration in high-performance computing (HPC) and edge devices.
Keynote talks will be given by celebrated computer scientists and engineers including Luca Cardelli (Oxford University), Bill Dally (Stanford University / NVIDIA), Mihaela van der Schaar (Cambridge University) and Mateo Valero (BSC). There will also be invited talks by EPI researchers Roger Espasa (Semidynamics) on the RISC-V Avispado core, John Davis (BSC) on building an open-source ecosystem for HPC, and Marc Casas (BSC) on accelerating deep neural network training.
The school chairpersons are Mateo Valero and Josep Fernandez (UPC), while the local organizing committee is led by Eduard Ayguadé, (BSC and UPC), and Fabrizio Gagliardi (BSC and ACM).
“EPI is revolutionising computer architecture to pave the way for Europe’s technological sovereignty. As part of the EPI training programme, this summer school provides the ideal introduction to some of the initiative’s main themes,” commented Jean-Marc Denis (Atos / SiPearl), chairman of the EPI board.
Upon completion of the school, all attendees will receive a certificate and a complimentary ACM student membership. Based on the scores obtained in the practical exercises, the best performing students will receive a certificate of honour and will also invited to interviews with industry sponsors, with a view to a possible internship.
The school includes a poster session, with a prize for the best poster.
Registration will be open until 15 July, and accepted candidates will be informed by 1 August.
To register, complete the registration form on the ACM Europe website.
The Initiative has successfully released EPAC1.0 Test Chip for fabrication
The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 28 partners from 10 European countries, with the goal of helping the EU achieve independence in HPC chip technologies and HPC infrastructure, is proud to announce that we have successfully released our EPAC1.0 Test Chip for fabrication.
One key segment of EPI activities is to develop and demonstrate fully European-grown processor IPs based on the RISC-V Instruction Set Architecture, providing power-efficient and high-throughput accelerator cores named EPAC (European Processor Accelerators). Using the RISC-V Instruction Set Architecture will allow leveraging open-source resources at hardware architecture and software level, as well as ensure independence from non-European patented computing technologies.
EPAC combines several accelerator technologies specialized for different application areas. The test chip, shown in figure 1 below, contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb. Each tile also contains a Home Node and L2 cache, designed respectively by Chalmers and FORTH, that provide a coherent view of the memory subsystem. The Stencil and Tensor accelerator (STX) was designed by Fraunhofer IIS, ITWM and ETH Zürich, and the variable precision processor (VRP) by CEA LIST. These specialized accelerators are connected with very high-speed network on chip and SERDES technology from EXTOLL.
The EPAC design was finalized by Fraunhofer IIS for chip integration in GLOBALFOUNDRIES 22FDX low-power technology and will be integrated and evaluated in the FPGA-based board designed by FORTH, E4 and the University of Zagreb. The successful fabrication of EPAC will showcase the next step in accelerator-based green HPC computing.
Figure 1 EPAC layout with VPU, STX and VRP accelerators with 25 mm2 in GF 22FDX technology
The outlook
The next generation of the EPAC accelerators and interfaces will be improved and refined for even higher performance and lower power levels in 12 nm technologies and below, and by adding a chiplet approach.
Jesus Labarta, BSC (EPAC Coordinator): I am really happy how partners with different backgrounds and motivations have been able to collaboratively develop this chip, putting all their efforts towards a collective success. It is a fully European design, driven by a vision of throughput-oriented computing and featuring characteristic that will result in high programmer productivity and achieve very high performance at low power and cost. Although just an initial Test Chip, it can be a significant step forward in HPC but also for edge and embedded applications.
Norbert Schuhmann, Fraunhofer IIS: The key challenge in this design and architecture was not only to achieve highest throughput and low power levels within the accelerators running on more than 1 GHz, but also to be in sync like in a concerto with memory accesses and data transport inside the chip and to the peripherals at rates above 200 Gbit/s.
Knut Hufeld, Senior Director R&D with Infineon and an Automotive Stream representative in EPI, talked about the developments in the stream with journalist Ralf Hartmann.
Infineon is known for microcontroller embedded real-time applications, so the European Processor Initiative EPI seems to be an ideal research field?
Definitely yes! With electric and autonomous driving as one of our main future issues, there will be an ever-increasing demand for computing power. Sophisticated driver assistance systems are one thing but new and highly complex applications like environment recognition in real-time will be another. Individual applications may be demanding, but operations like the fusion of sensor data from cameras, radar, or lidar systems are a real challenge. Conventional automotive microcontrollers are not capable to process the mass of information.
How could you bridge this impending gap in computing power?
One approach would be to take reliable automotive microprocessors like Infineon’s AURIX™ which are functional safe up to ASIL-D, and for the algorithms with an intense computing effort you just add processors from the consumer sector to be integrated with little or no adjustment or modification. This way, you create a safety/security configuration with the automotive-qualified real-time microprocessor controlling and monitoring the number crunchers from the consumer world.
Sounds like a makeshift constellation.
Indeed, using consumer parts is nothing but a work-around solution. First, because neither functional safety nor long-term reliability are ensured; second, they are not designed to the system, and moreover, they tend to use way too much energy.
What is the approach in EPI?
Regarding high-performance computing, HPC, the approach is to build a general-purpose processor, a GPP, which is designed for both high-level computing power and low-level energy consumption alike. This is where downsizing comes into play, which means that the number of computation kernels is reduced to what is necessary for automotive. We are talking about a derived variant of the GPP capable to serve typical automotive requirements on a minimum level and hence close the gap.
With its expertise in Automotive and as leader of Stream4 in EPI, which aspects does Infineon have to consider?
In the end, any technical achievement should be economically viable. Considering the high development costs, the challenge is to create downsized variants derived from HPC processors suitable for embedded constellations like in Automotive. Once they meet a high enough demand, they can be produced in sufficiently high unit numbers. The good news, recent developments indicate that the market will move in that direction, soon.
So, you bet on a win-win situation for HPC technology and the embedded sector?
As I said, the prospects are good. With a high demand for downsized variants and their mass production in the embedded sector, HPC can benefit from overall profitability generated by automotive as the driving belt. With this obvious solution, the high investments will pay off and HPC has a chance to become self-sustainable.
…which seems to be the key aspect in Stream4 as the mere automotive part in EPI?
That’s exactly it. Infineon coordinates the automotive part with partners like BMW, Elektrobit, Menta or Kalray, but also academic partners like Karlsruhe Institute of Technology, the Universities of Pisa and of Zagreb and Barcelona Supercomputing Centre. Our achievement is the implementation of a prototype automotive compute platform with integrated accelerators and other main IP blocks. Now, we are waiting for EPI partner SiPearl to come up with its first generation of HPC general-purpose processors. Then we can integrate and test them.
What will be your role in EPI’s upcoming evolutions?
We will still be present, albeit in a different way. In the first round, the Stream4 automotive team managed to accomplish promising results implementing the eHPC automotive platform, which reassures our pursued direction of development. In the upcoming round, we will adapt Infineon’s role towards an Industrial Advisor for embedded computing as an associated partner. This way, the EPI Initiative can take a full share of the limited financial funding resources for HPC technology, while we can shift our focus to setting up complementary projects under the European initiative KDT JU which then may give the opportunity for further synergies within EPI. In the meantime, we will, of course, meet our contractual obligations like exploiting the achievements of EPI. Regarding an effective promotion through face-to-face meetings, we hope that the current restrictions due to the COVID-19 pandemic will soon be lifted.
The European Processor Initiative (EPI) https://www.european-processor-initiative.eu/, a project with 28 partners from 10 European countries, with the goal of helping the EU achieve independence in HPC technologies is proud to announce that we have successfully booted Linux on our EPAC 1.0 core subset implemented on FPGA.
One key segment of EPI activities is to develop and demonstrate fully European processor IPs based on the RISC-V Instruction Set Architecture, providing power efficient and high throughput accelerator core named EPAC (European Processor Accelerator). Using RISC-V will allow leveraging open-source resources at hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.
First silicon implementation of EPAC 1.0 test chip is expected in the second half of 2021 and as an important technical milestone towards that goal, we have successfully booted Linux on a subset of EPAC 1.0 synthesized on FPGA. The FPGA design includes the Avispado RISC-V core, the Vector Processing Unit (VPU), the Network on Chip (NoC), the Shared L2 Cache with Coherence Home Node (L2HN), interrupt controllers, IO peripherals and several other components. This implementation will enormously speed-up software development on the EPI HPC architecture as well as testing and improving the architecture for next generations EPAC chips.
Figure 1 FPGA emulation and EPAC Software Development Vehicle block diagram
For the development of the EPI Accelerator Test Chip, we make extensive use of FPGA technologies to verify the RTL design of the Test Chip. The subset of EPAC 1.0 emulated on FPGA we use as Software Development Vehicle (SDV) to enable early software development before the actual Test Chip silicon comes back from the foundry.
The use of FPGAs enables the testing of RTL blocks with real and very complex software in timescales that are not tractable using pure RTL simulation. Also, it allowed us to stress memory coherence and several related corner cases. We have managed to boot Linux using the EPAC 1.0 system on FPGA and the system boots within a few dozens of seconds compared to weeks using pure simulation. The system is fully usable and interactive for system software and application development and it also includes Ethernet connectivity to enable running large and complex software packages, e.g., OpenMP, MPI.
This is a serious proof of concept that gives us the confidence of a functional and viable future product.
More details on the results can also be found on EPI YouTube Channel, where you can find the second episode of EPI Talks podcast, themed with booting Linux:
Channel: https://www.youtube.com/c/EuropeanProcessorInitiative/featured
Video: https://www.youtube.com/watch?v=X4klPnBjstI
This year’s HiPEAC conference was supposed to be held in beautiful Budapest, from January 18th to 20th 2021. However, due to the persistent pandemic conditions, it had to be moved to a digital edition.
European Processor Initiative’s consortium gladly accepted the opportunity to participate, both as a sponsor and with a tutorial given to the attendees. Our tutorial was held on Monday, January 18th, and it involved the following topics and presenters:
- Denis Dutoit, CEA: EPI overview and introduction to tutorial topics
- Sergio Saponara, UNIPI: Hardware security module in the EPI GPP
- Fabrizio Magugliani, E4: Update of the PCIe boards as development testbed for EPI
- Lilia Zaourar, Tanguy Sassolas, CEA: SESAM/VPSim: fast and highly configurable simulation framework for the EPI processor
- Andrea Bartolini, Giovanni Bambini, UNIBO: Emulating the power controller of the HPC power management systems
The tutorial was very well attended, and the attendees had a lot of interesting questions.
In addition to the tutorial, the EPI team has also hosted a virtual Brazen booth, where students, young researchers, and other prospective employees popped in to ask questions about the project. From the industrial side of EPI, Fabrizio Magugliani presented EPI in the industrial session, while Jurgen Becker attended the WRC workshop and gave an invited talk that involved EPI as well.
All of the presentations from HiPEAC given by EPI members can be found in our repository:
https://www.european-processor-initiative.eu/dissemination-material/epi-at-hipeac-2021/, while the tutorial video is also available on our YouTube Channel: https://www.youtube.com/watch?v=4AYDc6THtcM&t=9476s.
Finally, a shout-out to organizers: even though the team is more than eager to participate in the next one, hopefully live, HiPEAC conference, we are thankful to organizers for such a wonderful experience and the opportunity to share our views and ideas.
