EPI Forum 2024 - European Processor Initiative

Event recap BARCELONA, OCT 9-10

The European Processor Initiative held its first Forum on 9 and 10 October, 2024, in Barcelona, Spain.

EPI Forum gathered experts from the HPC ecosystem, stakeholders in the field and EPI researchers and engineers who discussed and presented EPI’s achievements so far and future developments in the Initiative.

Agenda of the event that was held can be found here: EPI FORUM AGENDA,

while the presentations and materials are available in our repository here:

https://www.european-processor-initiative.eu/dissemination-material/epi-forum-in-barcelona/

EPI Forum organizing committee wishes to thank the sponsors, speakers and panelists listed below for participating and making it a successful event. Stay tuned for announcements of the second EPI Forum next year!

EPI FORUM IS SPONSORED BY

EPI Forum speakers In alphabetical order

Andrea Bocco CEA

Andrea Bocco received the MSc and PhD degrees in computer engineering, in 2016 from the Politecnico di Torino (Turin, Italy), and 2020 from the INSA-Lyon (Lyon, France), respectively. He is a research engineer in CEA-List, Grenoble, France. His research interests include hardware and software computer arithmetic, floating-point arithmetic, with a particular focus on High-Performance-Computing hardware architectures for variable-precision floating-point applications.

Roger Espasa Semidynamics

Roger Espasa is the CEO and founder of Semidynamics, an IP supplier of two RISC-V cores, Avispado (in-order) and Atrevido (out-of-order) supporting the RISC-V vector extension and Gazzillion(tm) misses, both targeted at HPC and Artificial Intelligence. Prior to the foundation of the company, Roger was Technical Director/Distinguished Engineer at Broadcom leading a team designing a custom ARMv8/v7 processor on 28nm for the set-top box market. Before its experience at Broadcom, from 2002 to 2014, Roger led various x86 projects at Intel as Principal Engineer: SIMD/vector unit and texture sampler on Knights Ferry (45nm), L2 cache, texture sampler on Knights Corner (22nm), the out-of-order core on Knights Landing (14nm) and the Knights Hill core (10nm). From 1999 to 2001 he worked for the Alpha Microprocessor Group on a vector extension to the Alpha architecture. Roger got his PhD in Computer Science from Universitat Politècnica de Catalunya in 1997 and has published over 40 peer reviewed papers on Vector Architectures, Graphics/3D Architecture, Binary translation and optimization, Branch Prediction, and Media ISA Extensions. Roger holds 9 patents with 41 international filings.

Rod Evans NVIDIA

Rod Evans is NVIDIA’s Vice President for Supercomputing, Higher Education and AI for Europe, Middle East and Africa Rod is an accomplished entrepreneur and international business leader, with a proven track record of driving success across IT, software, and telecom businesses.

Rod’s 20+ years of international experience enables him to lead teams with passion, integrity, and confidence. A believer in leading by example, Rod’s strategic approach has resulted in significant growth in terms of headcount and revenue. He is a committed innovator with a keen interest in increasing awareness of AI’s potential. He works tirelessly to encourage the early adoption of AI by showcasing what it can do, how it works, and why implementing an AI strategy is critical.

He joined NVIDIA in 2018 and has overseen strong growth in the High-Performance Computing and Artificial Intelligence businesses at NVIDIA across Europe. Rod is a highly accomplished international business leader and draws on more than 30 years of experience in the IT industry.

Before joining NVIDIA, Rod led the European direct sales force at Intel Corporation and previously held European Vice President Positions at Silicon Graphics, Rackable Systems, Copan Systems and EMC. Currently based in Reading, United Kingdom; he has worked in the UK, USA, and Germany.

Rod is a British national and alumnus of Queen Mary University, London. After graduation, he began his career in sales from where he quickly progressed to senior management and C-Suite level roles

Tim Fischer ETHZ

Tim Fischer received his BSc and MSc degrees in Electrical Engineering and Information Technology from the Swiss Federal Institute of Technology Zurich (ETH Zurich) in 2018 and 2021, respectively. He is currently pursuing a Ph.D. in the Digital Circuits and Systems group at ETH Zurich, under the supervision of Prof. Luca Benini. He is also an active member of the PULP platform, an initiative known for its contributions to open-source IP development.

His primary research focuses on scalable and energy-efficient interconnects for both on-chip and off-chip communication. His work also expands to large-scale RISC-V architectures for high-performance computing (HPC) systems, with a particular emphasis on optimizing data movement in accelerators for improved efficiency and performance.

Alexandra Kourfali EuroHPC Joint Undertaking

Alexandra Kourfali is a Programme Manager of Research and Innovation at the EuroHPC Joint Undertaking, focused on the Technology pilar and managing the chips projects. She received her MSc degree in Computer Engineering from the University of Thessaly, Greece, and her Ph.D. in Computer Engineering from Ghent University, Belgium, in 2019. Previously she held academic appointments at Ghent University, Stuttgart University, the Barcelona Supercomputing Center, and the European Space Agency, and non-academic appointments at Thales, Belgium. Her interests include High-Performance Computing, reconfigurable computing, hardware reliability, and computer architectures with an emphasis on RISC-V

Mario Kovač UNIZG FER

Mario Kovač is a full professor at the Faculty of Electrical Engineering and Computing (FER), University of Zagreb, Croatia and Director of HPC Architectures and Applications Research Center at FER. He received his PhD in computer science and engineering from the same university in 1995. He was awarded Fulbright scholar award for Computer Science and Engineering Research that he spent at the University of South Florida, Tampa, USA between 1990 and 1994. His special focus was on efficient chip implementation of architectures for image, video and math computation processing that led to several chips including Jaguar chip. He holds several US and international patents in multimedia and architecture domains. His work on architectures and efficient execution was focused over time in several industry domains: multimedia systems, large national/cross-national health-care systems, electric cars and other. In 2008, Croatian President awarded him with the Medal of Honor “Order of Danica Hrvatska with the image of Ruđer Bošković” for special merit in science. His professional activities throughout years were always intertwined combination of science and industry activities. He was President/Vice-president of the Board and CxO of several organisations and companies where he was primarily involved in strategic management and R&D.

Eric Lalardie arm

After starting my career through the tech doors at Intel Corporation I moved to Arm in 1998 to help build its partner base, and develop long-term, multinational relationships that are helping to transform our digital future.

Arm’s open and diverse ecosystem has led me to running business across Europe, Russia, Israel, USA, Canada, India … giving me valuable insights into market trends and a deep understanding of technology requirements.

Engaged at the highest level within our ecosystem, from startups to multinationals, from research clusters to officials, I had been able to support and develop the semiconductor ecosystem in Europe.

I am a convinced European citizen. I had been supporting the EPI initiative since day 1 and look forward to strengthening the European semiconductor related players (HPC, Telco, Automotive…).

Filippo Mantovani BSC

Filippo Mantovani is an established researcher leading the Mobile and Embedded-based HPC group at the Barcelona Supercomputing Center (BSC). He holds a Ph.D. in Computer Science from the University of Ferrara, Italy, and has worked as a scientific associate at DESY in Zeuthen, Germany, and the University of Regensburg, Germany. His career has focused on computational physics and high-performance computing, contributing to projects like Janus, QPACE, and Mont-Blanc. Currently, he is involved in the FPGA prototyping tasks of RISC-V-based accelerators within the European Processor Initiative (EPI) and leads the collaboration between BSC and Etxe-tar to optimize high-throughput manufacturing systems.

Eric Monchalin Eviden, an Atos business

Eric Monchalin is Vice-President, Head of Machine Intelligence at Eviden and Chair of the European Processor Initiative. At Eviden, he is responsible for creating and finalizing new technological and business initiatives for the Big Data and Security Global Business Line. His career has been built on numerous R&D positions in the areas of embedded systems, communication, storage, AI, edge and high-performance computing. He is a technology-minded person who has a wide range of skills and technological knowledge and is fully focused on turning customers’ wishes into reality.

Philippe Notton SiPearl

Philippe Notton is the Founder and CEO of SiPearl, the European company building the high-performance low-power microprocessor dedicated to supercomputing and AI.

His original vision of SiPearl came in 2015 while he was leading a division of 2400 engineers at STMicroelectronics. In 2017, he joined Atos to help set up the European Processor Initiative (EPI) consortium, which aim to foster the return of high-performance microprocessor design to Europe. In June 2019, Philippe created SiPearl with the support of the European Union. In October 2023, SiPearl won an emblematic contract to equip JUPITER, the first exascale supercomputer in Europe.

With 7 R&D centers in France (Maisons-Laffitte, Grenoble, Massy, Sophia Antipolis), Germany (Duisburg), Italy (Bologna) and Spain (Barcelona), SiPearl employs more than 200 people.

Jean-Pierre Panziera Eviden, an Atos business

Jean-Pierre Panziera the Chief Technology Director for High Performance Computing at Eviden, an Atos business. He joined Bull, now part of Eviden, in 2009, and is responsible for future HPC hardware developments. He started his career at Elf-Aquitaine as a research developer for seismic processing. After joining a couple of startups in the Silicon Valley, he worked for 20 years at SGI where he held various position in the USA and in Europe, first as an HPC application specialist and later as a Chief Engineer.

He is also the Chairman of the ETP4HPC association which represents the HPC ecosystem in Europe and he is a member of EuroHPC Joint Undertaking Governing Board.

Jean-Pierre holds an engineer degree from Ecole Nationale Supérieure des Mines de Paris.

Daniele Piccarozzi AMD

Daniele Piccarozzi manages market development for AMD in the EMEA region, specialising in high-performance computing (HPC) and artificial intelligence (AI). With extensive experience in both technical and commercial roles, Daniele contributed to the design and deployment of major HPC installations in Europe, used for scientific research and industrial applications.

Craig Prunty SiPearl

Craig Prunty is Vice President Product Marketing at SiPearl. A product marketing expert in the global HPC market, he has spent the majority of his career in France and California with global semiconductor companies (Marvell Semiconductor, Cavium, AppliedMicro), contributing to the commercial success of several product lines. In his various positions, he has been engaged in industry consortiums and has built up a robust global network of partners

Prior to moving to SiPearl in May 2020, Craig was Marketing Director for Marvell Semiconductor’s server processors division in Santa Clara, California. He has successfully developed new markets including high-performance computing harnessing Arm technology.

A dual French and American national, Craig has a Master in Electrical Engineering from San Diego State University.

Stéphane Requena GENCI

Stéphane Requena is Director of Technology and Innovation at GENCI (France). Previously he has been during 10 years in charge of the HPC facilities at Institut Français du Pétrole and involved into optimisation and parallelisation of oil & gas (geology, seismic, reservoir modeling) and automotive applications. He also worked at CS a French service company in parallelising applications in the field of energy for EDF and CEA. At GENCI since 2007 he has been involved in several European projects including PRACE aisbl (as member of the Board of Directors), PRACE implementation projects (Prace-xIP), PPI4HPC (Public Procurement of HPC Innovative Solutions), Mont-Blanc (toward ARM based architectures used for HPC), EPI and EUPEX (toward designing European Processor technologies), EESI (European Exascale Software Initiative) and EXDCI (European eXtreme Data and Computing Initiative) in relation to the scientific and industrial applications roadmaps. He is also currently involved into EuroHPC as Chair of INFRAG and into Jules Verne consortium toward the 2nd EuroHPC Exascale system. At GENCI he is also in charge of the development of innovative services toward the use of AI, quantum computing, use of urgent computing for decision making, link with scientific instruments and the technical part of GENCI’s procurements for HPC, quantum and storage facilities.

David Snelling Fujitsu

Dr. David Snelling received his Doctor of Philosophy in Computer Architecture from Manchester University in 1993. His undergraduate and masters degrees are from the University of Denver. Prior to joining Fujitsu, he worked as a researcher and lecturer at the Universities of Manchester and Leicester. Dr. Snelling has regularly briefed industry analysts and the press on Fujitsu’s technical strategy, particularly in the areas of Artificial Intelligence, High Performance Computing, the Digital Annealer, and Quantum Computing. In this context, Dr. Snelling has been a strong supporter of Fujitsu’s ethically motivated and diversity focused approach to business and technology. Dr. Snelling’s latest role is Director of Quantum and High Performance Computing within the newly formed Center for Cognitive and Advanced Computing.

Mateo Valero Barcelona Supercomputing Center

Director of the Barcelona Supercomputing Center. His research focuses on high performance computing architectures. He has published approximately 700 papers, has served in the organization of more than 300 International Conferences and has given more than 600 invited talks. He has been honored with numerous awards, among them: Eckert-Mauchly, Seymour Cray, Charles Babbage, Harry H. Goode, ACM Distinguished Service Award; “Hall of Fame” award within the framework of the ICT European Program, selected as one of the 25 most influential European researchers in IT. National research awards: “Julio Rey Pastor” and the “Leonardo Torres Quevedo”; King James I Research Award from the Generalitat Valenciana; “Creu de Sant Jordi 2016”..Honored with “Condecoración de la Orden Mexicana del Águila Azteca” (2018), highest recognition granted by the Mexican Government for a non-Mexican citizen. Recognition for exceptional leadership in HPC at the “HPCWire Reader’s Choice Awards 2020” for “being an HPC pioneer since 1990 and the driving force behind the renaissance of European HPC independence.”Prof. Valero holds Honorary Doctorate by 11 Universities, is member of 10 academies and fellow of IEEE, ACM and Fellow of AAIA, Asia-Pacific Artificial Intelligence Association.

Etienne Walter Eviden, an Atos business

Etienne Walter is a senior expert and project manager in the R&D Division of Eviden, an Atos business. He is currently coordinating, as General Manager, the phase 2 of the European Processor Initiative and contributes to the coordination of the EUPEX Pilot project.

Etienne studied computer science and graduated as an engineer at Supelec (now CentraleSupelec – part of Paris-Saclay University ). He worked as software engineer, team manager and project manager in the telecommunication domain before joining the R&D division of Bull, now part of the Atos/Eviden group. He has been involved in HPC and Big Data projects for a number of years and was the project coordinator of H2020 projects Mont-Blanc 3 and Mont-Blanc 2020, while contributing to the preparation of EPI project.

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